14.6.1 Control Enable Register A
Note: Writes to this register while SYNCBUSY.SWRST is asserted will cause a bus
error.
Note: The state of the ENABLE bit at startup depends on the
setting of RAM_INIT_ENB.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CTRLA |
| Offset: | 0x0000 |
| Reset: | 0x2 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ENABLE | SWRST | ||||||||
| Access | R/W | R | |||||||
| Reset | x | 0 |
Bit 1 – ENABLE Enable TCMECC (Tightly Coupled Memory Error Correction Codes)
| Value | Description |
|---|---|
| 0 | Disable TCMECC - Turn off ECC error correction checking. |
| 1 | Enabled TCMECC - Turn on ECC error correction checking. |
Bit 0 – SWRST TCMECC Software Reset (Tightly Coupled Memory Error Correction Codes)
Write one to this bit to start a software reset of the module. The module will be disabled (ENABLE = 0) after the reset. Writing a zero has no effect. Due to bus synchronization, there is a delay from setting SWRST until the reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete.
Note: When writing a one to SWRST, no other bits in the same register will be
written, as SWRSTwill clear all the bits in the same register. Any
register write access during the ongoing reset will be discarded and a bus error
will be generated.
On Reading this bit:
| Value | Description |
|---|---|
| 0 | There is no reset operation ongoing |
| 1 | The reset operation is ongoing |