PIC32CZ CA80/CA90 Family

14.6.4 Interrupt Enable Clear Register

Note:

A read of this register shows whether interrupts are Enabled (1) or Disabled (0). Therefore, a write of a 1 to a bit then a read of the bit will return the interrupt is disabled (bit is zero).
Writing a one to any bit will disable the corresponding interrupt. Writing a zero will have no effect.
Writes to this register while SYNCBUSY.SWRST is asserted will cause a bus error.

Table 14-6. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	INTENCLR
Offset:	0x000C
Reset:	0x00000000
Property:	PAC Write-Protection


Bit	31	30	29	28	27	26	25	24
								FLTCAPEN
Access								R/W
Reset								0


Bit	23	22	21	20	19	18	17	16
						D1ECCECNTEN	D1DERREN	D1SERREN
Access						R/W	R/W	R/W
Reset						0	0	0


Bit	15	14	13	12	11	10	9	8
						D0ECCECNTEN	D0DERREN	D0SERREN
Access						R/W	R/W	R/W
Reset						0	0	0


Bit	7	6	5	4	3	2	1	0
						IECCECNTEN	IDERREN	ISERREN
Access						R/W	R/W	R/W
Reset						0	0	0

Bit 24 – FLTCAPEN Fault Capture Interrupt Enable Bit Disable

Value	Description
0	Writing a zero to this bit has no effect
1	CLEAR the ENABLE bit (FLTCAPEN) for the interrupt FTLCAP.

Bit 18 – D1ECCECNTEN D1TCM ECC Error Count Interrupt Enable Bit Disable

Value	Description
0	Writing a zero to this bit has no effect.
1	CLEAR the ENABLE bit (D1ECCECNTEN) for the interrupt D1ECCECNT.

Bit 17 – D1DERREN D1TCM Double Bit Error Detection Interrupt Enable Bit Disable

Value	Description
0	Writing a zero to this bit has no effect.
1	CLEAR the ENABLE bit (D1DERREN) for the interrupt D1DERR.

Bit 16 – D1SERREN D1TCM Single Bit Error Correction Interrupt Enable Bit Disable

Value	Description
0	Writing a zero to this bit has no effect.
1	CLEAR the ENABLE bit (D1SERREN) for the interrupt D1SERR.

Bit 10 – D0ECCECNTEN D0TCM ECC Error Count Interrupt Enable Bit Disable

Value	Description
0	Writing a zero to this bit has no effect.
1	CLEAR the ENABLE bit (D0ECCECNTEN) for the interrupt D0ECCECNT.

Bit 9 – D0DERREN D0TCM Double Bit Error Detection Interrupt Enable Bit Disable

Value	Description
0	Writing a zero to this bit has no effect.
1	CLEAR the ENABLE bit (D0DERREN) for the interrupt D0DERR.

Bit 8 – D0SERREN D0TCM Single Bit Error Correction Interrupt Enable Bit Disable

Value	Description
0	Writing a zero to this bit has no effect.
1	CLEAR the ENABLE bit (D0SERREN) for the interrupt D0SERR.

Bit 2 – IECCECNTEN ITCM ECC Error Count Interrupt Enable Bit Disable

Value	Description
0	Writing a zero to this bit has no effect.
1	CLEAR the ENABLE bit (IECCECNTEN) for the interrupt IECCECNT.

Bit 1 – IDERREN ITCM Double Bit Error Detection Interrupt Enable Bit Disable

Value	Description
0	Writing a zero to this bit has no effect.
1	CLEAR the ENABLE bit (IDERREN) for the interrupt IDERR.

Bit 0 – ISERREN ITCM Single Bit Error Correction Interrupt Enable Bit Disable

Value	Description
0	Writing a zero to this bit has no effect.
1	CLEAR the ENABLE bit (ISERREN) for the interrupt ISERR.

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