14.6.2 Control Enable Register B
Note:
- Writes to this register while SYNCBUSY.SWRST is asserted will cause a bus error.
- ECC error counters are reset to zero when the corresponding error counter is disabled.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CTRLB |
| Offset: | 0x0004 |
| Reset: | 0x00070707 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| D1ERCNTDIS | D0ERCNTDIS | IERCNTDIS | DWAITSTEN | IWAITSTEN | |||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| D1ERRCNT[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| D0ERRCNT[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| IERRCNT[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | |
Bit 30 – D1ERCNTDIS D1TCM Error Counter Disable
| Value | Description |
|---|---|
| 0 | Enable, D1TCM ERROR COUNTER is enabled |
| 1 | Disable,D1TCM ERROR COUNTER is disabled, no D1ECCECNT interrupts will be generated |
Bit 29 – D0ERCNTDIS D0TCM Error Counter Disable
| Value | Description |
|---|---|
| 0 | Enable, D0TCM ERROR COUNTER is enabled |
| 1 | Disable,D0TCM ERROR COUNTER is disabled, no D0ECCECNT interrupts will be generated |
Bit 28 – IERCNTDIS ITCM Error Counter Disable
| Value | Description |
|---|---|
| 0 | Enable, ITCM ERROR COUNTER is enabled |
| 1 | Disable, ITCM ERROR COUNTER is disabled, no IECCECNT interrupts will be generated |
Bit 25 – DWAITSTEN D1TCM and D0TCM One Wait State Enable
| Value | Description |
|---|---|
| 0 | D1TCM and D0TCM no wait states |
| 1 | D1TCM and D0TCM one wait state |
Bit 24 – IWAITSTEN ITCM One Wait State Enable
| Value | Description |
|---|---|
| 0 | ITCM no wait states |
| 1 | ITCM one wait state |
Bits 23:16 – D1ERRCNT[7:0] D1TCM Error Maximum Count (default0x7)
Counts the number of ECC errors. When the count expires a flag/interrupt (D1ECCECNT) is set.
Bits [7:3] are user programmable, bits [2:0] are hard coded to 0x7.
Enabled/disabled by D1ERCNTDIS.
Bits 15:8 – D0ERRCNT[7:0] D0TCM Error Maximum Count (default0x7)
Counts the number of ECC errors. When the count expires a flag/interrupt (D0ECCECNT) is set.
Bits [7:3] are user programmable, bits [2:0] are hard coded to 0x7.
Enabled/disabled by D0ERCNTDIS.
Bits 7:0 – IERRCNT[7:0] ITCM Error Maximum Count (default0x7)
Counts the number of ECC errors. When the count expires a flag/interrupt (IECCECNT) is set.
Bits [7:3] are user programmable, bits [2:0] are hard coded to 0x7.
Enabled/disabled by IERCNTDIS.