14.6.6 Interrupt Flag Status and Clear

Note:
  1. Writing a one to any bit will clear the corresponding interrupt flag. Writing a zero has no effect.
  2. Writes to this register while the SYNCBUSY.SWRST is asserted with cause a bus error.
Note: Subsequent to an interrupt flag being cleared, the flag must be read back to verify the clear before exiting the ISR. Failure to do this can result in duplicate interrupts.
Table 14-8. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit——
Name: INTFLAG
Offset: 0x0014
Reset: 0x00000000

Bit 3130292827262524 
        FLTCAP 
Access R/W 
Reset 0 
Bit 2322212019181716 
      D1ECCECNTD1DERRD1SERR 
Access R/WR/WR/W 
Reset 000 
Bit 15141312111098 
      D0ECCECNTD0DERRD0SERR 
Access R/WR/WR/W 
Reset 000 
Bit 76543210 
      IECCECNTIDERRISERR 
Access R/WR/WR/W 
Reset 000 

Bit 24 – FLTCAP Fault Capture Interrupt Flag

ValueDescription
0No fault capture has occurred.
1A fault capture has occurred from the previous address match.

Bit 18 – D1ECCECNT D1TCM ECC Error Count Interrupt Flag

ValueDescription
0The D1TCM error count has not expired.
1The D1TCM error count defined in CTRLB.D1ERRCNT has expired.

Bit 17 – D1DERR D1TCM Double Bit Error Detection Interrupt Flag

ValueDescription
0A double error detection has not occurred.
1A double error detection has occurred from the previous address match for D1TCM.

Bit 16 – D1SERR D1TCM Single Bit Error Correction Interrupt Flag

ValueDescription
0A single bit correction has not occurred.
1A single error correction has occurred from the previous address match for D1TCM.

Bit 10 – D0ECCECNT D0TCM ECC Error Count Interrupt Flag

ValueDescription
0The D0TCM error count has not expired.
1The D0TCM error count defined in CTRLB.D0ERRCNT has expired.

Bit 9 – D0DERR D0TCM Double Bit Error Detection Interrupt Flag

ValueDescription
0A double error detection has not occurred.
1A double error detection has occurred from the previous address match for D0TCM.

Bit 8 – D0SERR D0TCM Single Bit Error Correction Interrupt Flag

ValueDescription
0A single error correction has not occurred.
1A single error correction has occurred from the previous address match for D0TCM.

Bit 2 – IECCECNT ITCM ECC Error Count Interrupt Flag

ValueDescription
0The ITCM error count has not expired.
1The ITCM error count defined in CTRLB.IERRCNT has expired.

Bit 1 – IDERR ITCM Double Bit Error Detection Interrupt Flag

ValueDescription
0A double error detection has not occurred.
1A double error detection has occurred from the previous address match for ITCM.

Bit 0 – ISERR ITCM Single Bit Error Correction Interrupt Flag

ValueDescription
0A single error correction has not occurred.
1A single error correction has occurred from the previous address match for ITCM.