14.6.15 DnTCM Fault Error Capture Address Register, n = 0,1
Note:
- Writes to this read-only register will produce a bus error.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | DFLTCAPn |
| Offset: | 0x38 + n*0x10 [n=0..1] |
| Reset: | 0x00000000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| DTCMMASTER[3:0] | |||||||||
| Access | R | R | R | R | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| FLTADR[16] | |||||||||
| Access | R | ||||||||
| Reset | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| FLTADR[15:8] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FLTADR[7:0] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 31:28 – DTCMMASTER[3:0] Host ID of the Requester of the Current Error Access
| Value | Description |
|---|---|
| 0b0000 | Instruction fetch |
| 0b0001 | Data access |
| 0b0010 | Vector fetch on automated exception entry |
| 0b0011 | AHB client access |
| 0b0100 | Debugger access |
| 0b0101 | MBIST access |
| 0b1001 | Software data access from store queue |
| 0b1011 | AHB client access from store queue |
| 0b1100 | Debugger access from store queue |