14.6.3 Synchronization Register
Note:
- Writes to this read-only register will cause a bus error.
- Writes to any registers while SYNCBUSY.SWRST is asserted will produce a bus error.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | SYNCBUSY |
| Offset: | 0x0008 |
| Reset: | 0x00000000 |
| Property: | – |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FLTEN | SWRST | ||||||||
| Access | R | R | |||||||
| Reset | 0 | 0 |
Bit 1 – FLTEN Fault Injection Enabled Synchronization Busy
This flag is set by hardware during the bus synchronization of the FLTCTRL register. It is cleared when bus synchronization is complete. No writes are allowed to FLTCTRL when this flag is set.
Bit 0 – SWRST Software Reset Synchronization Busy
This flag is set by hardware during the bus synchronization of the CTRLA.SWRST. It is cleared when bus synchronization is complete. No writes are allowed to CTRLA when this flag is set.