14.6.5 Interrupt Enable Set

Note:
  1. A read of this register shows whether interrupts are Enabled ‘1’ or Disabled ‘0’. Therefore, a write of a 1 to a bit then a read of the bit will return the interrupt is enabled (bit is one).
  2. Writing a one to any bit will enable the corresponding interrupt. Writing a zero will have no effect.
  3. Writes to this register while SYNCBUSY.SWRST is asserted will cause a bus error.
Table 14-7. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit——
Name: INTENSET
Offset: 0x0010
Reset: 0x00000000
Property: PAC Write-Protection

Bit 3130292827262524 
        FLTCAPEN 
Access R/W 
Reset 0 
Bit 2322212019181716 
      D1ECCECNTEND1DERREND1SERREN 
Access R/WR/WR/W 
Reset 000 
Bit 15141312111098 
      D0ECCECNTEND0DERREND0SERREN 
Access R/WR/WR/W 
Reset 000 
Bit 76543210 
      IECCECNTENIDERRENISERREN 
Access R/WR/WR/W 
Reset 000 

Bit 24 – FLTCAPEN Fault Capture Interrupt Enable

ValueDescription
0Writing a zero to this bit has no effect
1SET the ENABLE bit (FLTCAPEN) for the interrupt FTLCAP.

Bit 18 – D1ECCECNTEN D1TCM ECC Error Count Interrupt Enable

ValueDescription
0Writing a zero to this bit has no effect.
1SET the ENABLE bit (D1ECCECNTEN) for the interrupt D1ECCECNT.

Bit 17 – D1DERREN D1TCM Double Bit Error Detection Interrupt Enable

ValueDescription
0Writing a zero to this bit has no effect.
1SET the ENABLE bit (D1DERREN) for the interrupt D1DERR.

Bit 16 – D1SERREN D1TCM Single Bit Error Correction Interrupt Enable

ValueDescription
0Writing a zero to this bit has no effect.
1SET the ENABLE bit (D1SERREN) for the interrupt D1SERR.

Bit 10 – D0ECCECNTEN D0TCM ECC Error Count Interrupt Enable

ValueDescription
0Writing a zero to this bit has no effect.
1SET the ENABLE bit (D0ECCECNTEN) for the interrupt D0ECCECNT.

Bit 9 – D0DERREN D0TCM Double Bit Error Detection Interrupt Enable

ValueDescription
0Writing a zero to this bit has no effect.
1SET the ENABLE bit (D0DERREN) for the interrupt D0DERR.

Bit 8 – D0SERREN D0TCM Single Bit Error Correction Interrupt Enable

ValueDescription
0Writing a zero to this bit has no effect.
1SET the ENABLE bit (D0SERREN) for the interrupt D0SERR.

Bit 2 – IECCECNTEN ITCM ECC Error Count Interrupt Enable

ValueDescription
0Writing a zero to this bit has no effect.
1SET the ENABLE bit (IECCECNTEN) for the interrupt IECCECNT.

Bit 1 – IDERREN ITCM Double Bit Error Detection Interrupt Enable

ValueDescription
0Writing a zero to this bit has no effect.
1SET the ENABLE bit (IDERREN) for the interrupt IDERR.

Bit 0 – ISERREN ITCM Single Bit Error Correction Interrupt Enable

ValueDescription
0Writing a zero to this bit has no effect.
1SET the ENABLE bit (ISERREN) for the interrupt ISERR.