35.6.8.2 Control B

Write to this register only when SYNCBUSY.CTRLB = 0, otherwise a bus error will result.
Table 35-11. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit——
Name: CTRLB
Offset: 0x04
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected, Write-Synchronized

Bit 3130292827262524 
       LINCMD[1:0] 
Access R/WR/W 
Reset 00 
Bit 2322212019181716 
 FIFOCLR[1:0]    RXENTXEN 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 15141312111098 
   PMODE  ENCSFDECOLDEN 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 76543210 
  SBMODE   CHSIZE[2:0] 
Access R/WR/WR/WR/W 
Reset 0000 

Bits 25:24 – LINCMD[1:0] LIN Command

These bits define the LIN header transmission control.

ValueDescription
0x0Normal USART transmission.
0x1Break field is transmitted when DATA is written.
0x2Break, sync, and identifier are automatically transmitted when DATA is written with the identifier.
0x3Reserved
Note:
  1. This field is only valid in LIN Host mode, (CTRLA.FORM = 0x2).
  2. These bits are strobe bits and will always read back as zero.
  3. These bits are not enable-protected.

Bits 23:22 – FIFOCLR[1:0] FIFO Clear

When these bits are set, the corresponding FIFO will be cleared. The bits will automatically clear when SYNCBUSY.CTRLB = 0.

ValueNameDescription
0x0NONENo action
0x1TXFIFOClear TX FIFO
0x2RXFIFOClear RX FIFO
0x3BOTHClear both TX/RX FIFO
Note: These bits are not enable-protected.

Bit 17 – RXEN Receiver Enable

ValueDescription
0x0The receiver is disabled or being enabled.
0x1The receiver is enabled or will be enabled when the USART is enabled.
Note:
  1. Writing ‘0x0’ to this bit will disable the USART receiver. Disabling the receiver will flush the receive buffer, FIFO if enable and clear the FERR, PERR, and BUFOVF bits in the STATUS register.
  2. Writing ‘0x1’ to CTRLB.RXEN when the USART is disabled will set CTRLB.RXEN immediately. When the USART is enabled, CTRLB.RXEN will be cleared, and SYNCBUSY.CTRLB will be set and remain set until the receiver is enabled.
  3. When the receiver is enabled, CTRLB.RXEN will read back as ‘0x1’. Writing ‘0x1’ to CTRLB.RXEN when the USART is enabled will set SYNCBUSY.CTRLB, which will remain set until the receiver is enabled, and the CTRLB.RXEN will read back as ‘0x1’.
  4. This bit is not enable-protected.

Bit 16 – TXEN Transmitter Enable

ValueDescription
0x0The transmitter is disabled or being enabled.
0x1The transmitter is enabled or will be enabled when the USART is enabled.
Note:
  1. Writing ‘0x0’ to this bit will disable the USART transmitter. Disabling the transmitter will not become effective until ongoing and pending transmissions are completed. Subsequent CPU TX DATA writes will be ignored.
  2. Writing ‘0x1’ to CTRLB.TXEN when the USART is disabled will set CTRLB.TXEN immediately, When the USART is enabled, CTRLB.TXEN will be cleared, and SYNCBUSY.CTRLB will be set and remain set until the transmitter is enabled. When the transmitter is enabled, CTRLB.TXEN will read back as ‘0x1’.
  3. Writing ‘0x1’ to CTRLB.TXEN when the USART is enabled will set SYNCBUSY.CTRLB, which will remain set until the transmitter is enabled, and CTRLB.TXEN will read back as ‘0x1’.
  4. This bit is not enable-protected.

Bit 13 – PMODE Parity Mode

This bit selects the type of parity used when parity is enabled, (CTRLA.FORM = 0x1, 0x5, 0x7').

ValueDescription
0x0Even parity.
0x1Odd parity.
Note:
  1. The transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value for the incoming data and parity bit, compare it to the parity mode and, if a mismatch is detected, STATUS.PERR will be set.
  2. This bit is not synchronized.

Bit 10 – ENC Encoding Format

This bit selects the data encoding format for IrDA.

ValueDescription
0x0Data is not encoded.
0x1Data is IrDA encoded.
Note:
  1. This bit is not synchronized.
  2. CTRLA.FORM = 0x0 and CTRLA.SAMPR = 0x0.

Bit 9 – SFDE Start of Frame Detection Enable

This bit controls whether the start-of-frame detector will wake up the device when a start bit is detected on the RxD line.

ValueINTENSET.RXSINTENSET.RXCDescription
0x0XXStart-of-frame detection disabled.
0x10x00x0Reserved
0x10x00x1Start-of-frame detection enabled. RXC wakes up the device from all sleep modes.
0x10x10x0Start-of-frame detection enabled. RXS wakes up the device from all sleep modes.
0x10x10x1Start-of-frame detection enabled. Both RXC and RXS wake up the device from all sleep modes.
Note: This bit is not synchronized.

Bit 8 – COLDEN Collision Detection Enable

This bit enables collision detection.

ValueDescription
0x0Collision detection is not enabled.
0x1Collision detection is enabled.
Note:
  1. Collision detect is confined to CTRLA.FORM = 0x7, ISO 7816 but is also possible for applications utilizing 2-wire RS485 half-duplex arrangements where the external RS485 transceiver Rx and Tx are enabled at the same time to form a loop back.
  2. This bit is not synchronized.
  3. When collision is enabled and detected, hardware automatically disables the transmitter, CTRLB.TXEN = 0, and sets STATUS.COLL = 1.

Bit 6 – SBMODE Stop Bit Mode

This bit selects the number of stop bits transmitted.

ValueDescription
0x0One stop bit.
0x1Two stop bits.
Note: This bit is not synchronized.

Bits 2:0 – CHSIZE[2:0] Character Size

These bits select the number of bits in a character.

ValueDescription
0x08 bits
0x19 bits
0x2-0x4Reserved
0x55 bits
0x66 bits
0x77 bits
Note: These bits are not synchronized.