1.1.1.9.3 DFE Calibration

DFE calibration is carried out by an embedded sequence function, which is optimized to avoid local minima, achieve predictable results, allow for low area, and operate at high clock speeds. It adjusts the feedback coefficients in response to the eye-area. The sequence of the function is used to determine the width, height, and center of the eye opening. DFE Calibration is carried out by a algorithm that adjusts the feedback coefficients (from H1 to H5) by trial-and-error in response to the eye-area of the eye_monitor. The algorithm operates on one dimension (a single coefficient) at a time. It takes a step of size 1 in the positive direction and then the negative direction that is H1+1 and H1-1. If the area improves on either step, it continues to take another step in the same direction. If both directions yield a lower area, it continues to the next coefficient with the same step size. After failing to improve the area on all coefficients, it increases the step size and continue. If the area is improved, the step size immediately reduces to 1. For more information, see PolarFire FPGA Transceiver Decision Feedback Equalization Application Note.

Dependent on the specific design targets chosen through Libero, the design can be configured in one of two modes that require calibration of the receiver.

In CTLE only mode, CTLE solution is executed to optimize gain/frequency settings using CTLE Frequency Response and DC Offset calibration.

In CTLE/DFE mode, CTLE calibration is first run to optimize gain/frequency settings using CTLE Frequency Response and DC Offset calibration. DFE calibration is then run for centering and coefficients.

DFE is optionally programmed to be used in several operations. Full DFE calibration autonomously calibrates to the best found DFE coefficients for optimized data eye centering. These are controlled by Libero specified options.

DFE can also be set in static mode where the user can specify the exact DFE coefficients required by the design. DFE Coefficients are set through PDC commands (see DFE Coefficients) can be used from the register rather than from calibration. This mode does not expose the CALIB_REQ pin or any of the pins to trigger auto-calibration or incremental calibration.

Incremental DFE is another option of calibration to incrementally improve the performance of the DFE path. A specific PF_XCVR_ERM core is generated by Libero which, exposes the required pins to trigger the incremental calibration.

Two algorithms are available for re-calibration:

• Data Eye clock centering Re-calibration
• DFE Coefficient Re-calibration.

Both algorithms do eye-centering, however, they are independent operations. Full calibration and Static calibration are mutually exclusive and Incremental calibration of any of the two algorithms can only be applied after at least one ‘Full calibration’.

Users can enable one or both choices in PF_XCVR_ERM configurator depending on the mode of operation and the receiver calibration options selected.

The calibration blocks are used at power-up calibration and user demanded recalibration. These are Libero configured. The following table lists the summary of mode of operations.

Examples of the specific types of calibration are:

ON_DEMAND

The receiver does not calibrate automatically. The user must initiate an on-demand calibration using either the wires on the XCVR interface or over the DRI. If the specific design performs dynamic reconfiguration using DRI, then the user routine must perform a recalibration each time the XCVR locks to a new data rate and/or data pattern.

In CDR modes where data rate ≤ 10312.5 Mbps, the device performs DC offset calibration of the CDR and the CTLE calibration when the user toggles the CALIB_REQ port. When calibration is completed, the best DC offset and RX CTLE settings are applied to the receiver.

In DFE modes where data rate > 10312.5 Mbps, the device performs the same optimization as in CDR mode with the addition on performing full DFE calibration of the DFE coefficients. When calibration is completed the best DC offset, RX CTLE, and DFE coefficient settings are applied to the receiver.

To successfully complete the RX (CTLE) calibration process, the reference clocks must be stable and free running at device power-up and valid data must be present at the transceiver Rx input buffers. The data should be approximately the actual data that is received but does not need to be any particular data pattern. However, for DFE, calibration can be dependent on the data pattern used at DFE calibration. For example, JESD204B startups with a continuous K28.5 stream, then later shifts to actual 8b10b data. This is a change in data pattern and may impact calibrated DFE coefficients.

The transceiver component is generated by the Libero software to include enhanced receiver management logic to control the proper calibration of the receiver, see Enhanced Receiver Management. The ERM manages calibration providing the user design a streamlined procedure to initiate and monitor calibration from the fabric interface. These calibration modes have higher power than using the NONE selection as the EYE MONITOR circuitry is active during these modes.

Incrementally Recalibrate Data Eye

This is a method to improve the performance of the DFE path after an initial calibration is performed. This recalibration is intended to improve the data eye for most gradients that typically occur due to temperature or voltage changes within the system.

The recalibration is performed by using the DC offset values for the DFE path that were determined by the prior offset calibration as the initial values and then perform the clock phase centering function. The calibration is marked as complete, when the area compute function is completed in the silicon/FPGA. This is indicated by driving the output signal LANE#_DATA_EYE_CALIBRATION_DONE to high.

Incrementally Recalibrate DFE Co-efficients

In this recalibration, the DFE co-efficients are recomputed in an incremental manner when an initial calibration is performed (on-demand or on initial power up).

The recalibration is performed by using the DC-offset values for the DFE path that were determined during a prior offset calibration as the initial value. The prior computed DFE coefficient values (H1-H5) are used as the starting coefficients for the DFE calibration. This reduces the DFE computation time. The calibration is marked as complete when the DFE calibration is completed in the silicon/FPGA. The output signal LANE#_DFE_COEFF_RECALIBRATION_DONE is driven high when the calibration is completed.

ON_DEMAND_AND_FIRST_LOCK

It is same as On_Demand with the addition of auto calibration. Auto calibration occurs automatically the first time the CDR locks to data. The user can also on-demand initiate a calibration event using wires on the XCVR interface or over the DRI.