3.6.2.2.2 SINGLE_HDL_OUTPUT_FILE
(Ask a Question)When set to 1, this Tcl parameter constrains SmartHLS-generated Verilog RTL and VHDL wrapper modules to a single Verilog file (<Project Name>.v) and a single VHDL file (<Project Name>.vhd) respectively. By default, each Verilog top-level module (and its child modules) is printed to a separate output file (<Project Name>_<Top-Level Name>.v), and each VHDL wrapper module of a top-level is printed to a separate VHDL file (<Project Name>_<Top-Level Name>.vhd).
- Category
- HLS Constraints
- Value Type
- Boolean
- Valid Values
- 0, 1
- Default Value
SINGLE_HDL_OUTPUT_FILE 0- Dependencies
- None
- Applicable Flows
- All devices and flows
- Test Status
- Actively in-use
- Examples
set_parameter SINGLE_HDL_OUTPUT_FILE 1