3.6.2.1 Constraints Manual

SmartHLS™ accepts user-provided constraints that impact the automatically generated hardware. These constraints can be specified using the SmartHLS IDEand are stored in the Tcl configuration file config.tcl located in your project directory. This section provides information about the constraints available for SmartHLS. The main constraints available from the SmartHLS IDE are:

• Set target clock period: 3.6.2.2.1 CLOCK_PERIOD
• Print the HDL output to a single output file: 3.6.2.2.2 SINGLE_HDL_OUTPUT_FILE
• Set custom config file: 3.6.2.2.3 set_custom_config_file
• Set test bench file: 3.6.2.2.4 set_custom_test_bench_file
• Set test bench module: 3.6.2.2.5 set_custom_test_bench_module
• Set operation latency: 3.6.2.2.6 set_operation_latency
• Set FPGA family and device: 3.6.2.2.7 set_project
• Set resource constraint: 3.6.2.2.8 set_resource_constraint
• Set FPGA synthesis top-level module: 3.6.2.2.9 set_synthesis_top_module
• Set FPGA synthesis top-level file: 3.6.2.2.10 set_synthesis_top_module_file

A few debugging constraints are available from the SmartHLS IDE:

• Stalling input/output FIFOs in CoSimulation: 3.6.2.3.1 COSIM<INPUT|OUTPUT>_FIFO_STALL_PROB
• Keep signals with no fanout: 3.6.2.3.2 KEEP_SIGNALS_WITH_NO_FANOUT
• Insert simulation assertions (for debugging): 3.6.2.3.3 VSIM_ASSERT