3.5.1.22.3 Running SoC Features

Base SoC Project Programming / Cross-Compilation

SmartHLS™ comes with a pre-built bitstream for PolarFire® SoC Icicle Kit and PolarFire Video Kit, containing a base SoC design. The base SoC design can be programmed to a board in order to cross-compile and test user software on Linux running on the board for the Icicle Kit, and baremetal for the MiV_RV32 on the PolarFire FPGA. . To program this base SoC, navigate to the SmartHLS tab, and select RISC-V SoC Features > Base SoC with no SoC Accelerators > Program board with prebuilt bitstream.

In the same sub-menu, there is an option to cross-compile the project software into a binary for RISC-V (Cross-compile software for RISC-V), as well as an option to move this binary to an attached Icicle Kit and run it (Run software without accelerators). In order to run software on an attached Icicle Kit, some preliminary setup steps are required, see Icicle Kit Setup Instructions.

Reference SoC Generation

SmartHLS™ is also capable of taking the hardware accelerators it generates, and integrating them with the Microprocessor Sub-System (MSS) on a PolarFire® SoC FPGA (currently only supports PolarFire SoC Icicle Kit to create a reference SoC design in SmartDesign. This is done by taking the base SoC project, adding hardware accelerators as SmartDesign HDL+ cores, and connecting the components using an AXI4 interconnect. To generate this reference SoC design, navigate to the SmartHLS tab, and select RISC-V SoC Features > Reference SoC with HLS Accelerator(s) > Generate Libero Design. For more information on the architecture of this reference SoC, see 3.5.3.4 SmartHLS™ Reference SoC.

Important:

In order for accelerators to be automatically integrated into a reference SoC, they must have only AXI4 Target and AXI4 Initiator hardware interfaces. This can be accomplished by specifying the correct interface pragmas (see interface pragmas section in the Pragmas Manual). For more information on the accelerator hardware interface see 3.5.1.18 Top-Level RTL Interface.

Running the Reference SoC

In the same sub-menu, there are also options to run synthesis and place and route for the reference SoC, which can be used to check timing and resource usage of each accelerator as well as the whole SoC. There are also options to generate a bitstream and program it to an attached Icicle Kit. Finally, the Run software with accelerators option combines the input software with the generated accelerator drivers, and creates a software binary that can run on Linux in the Icicle MSS and drive the SmartHLS™ accelerators on the fabric. In order to run software on an attached Icicle Kit, some preliminary steps are required, see Icicle Kit Setup Instructions. For an example on how to do this with the MiV_RV32 on the PolarFire® Video Kit, see PolarFire Video Kit Setup Instructions.