3.5.1.24.1 Background: LLVM Internal Representation used by SmartHLS™

The instructions displayed in the Schedule Viewer are from the LLVM compiler that SmartHLS is built on. These assembly-like instructions are called LLVM intermediate representation (IR) . Some understanding of the LLVM IR is beneficial when using the Schedule Viewer.

For example, given the 32-bit code:

result = a + b - 5 

This C++ code could be represented as instructions in LLVM IR as:

%0 = add i32 %a, %b
%result = sub i32 %0, 5

In LLVM IR, intermediate variables are prefixed with a “%”. Each operation (add/sub) includes the bitwidth “i32” indicating 32-bit integer. The add operands are %a + %b and the result is stored in a temporary 32-bit variable %0. The subtract operands are %0 – 5 and the result is stored in the variable %result.

Basic blocks are also important concepts in LLVM IR. A basic block is a group of instructions that always run together with a single entry point at the beginning and a single exit point at the end. A basic block in LLVM IR always has a label at the beginning and a branching instruction at the end (br, ret, etc.). Control flow occurs between basic blocks.

Here the body.0 basic block performs some operations and then branches unconditionally to another basic block labeled body.1.

body.0:
  %0 = add i32 %a, %b
  %result = sub i32 %0, 5
  br label %body.1

All of the basic blocks and instructions shown in the Scheduler Viewer are directly from the LLVM IR optimized by SmartHLS before being compiled into Verilog.