v2024.1

1 What's New
Information about what is new in Libero SoC Design Suite
2 Download Help
Information to help you download the Libero SoC Design Suite documentation
3 SmartHLS Compiler
Information about SmartHLS Compiler
- 3.1 Overview
  Welcome to the User Manual of SmartHLS.
- 3.2 Getting Started
  Information and resources to help you get started using SmartHLS as quickly as possible.
- 3.3 Technical Support
- 3.4 Quick Start Tutorial
  Learn how to use some of the major features and optimization techniques of SmartHLS.
- 3.5 Working with SmartHLS
  Information and resources to help you work with SmartHLS.
- 3.6 Additional References
  Information about the additional references to help you use SmartHLS.
- 3.7 SmartHLS™ Examples
  Information about SmartHLS examples.
4 Installation and Licensing
Information about Libero SoC software installation and licensing
5 Design Flow
Information about Design Flow
6 Block Flow
Information about Block Flow
7 SmartDesign
Information about SmartDesign
8 Netlist Viewer
Information about Netlist Viewer
9 I/O Editor
Information about I/O Editor
10 PDC Commands
Information about PDC commands for all families
11 Chip Planner
Information about Chip Planner
12 Timing Constraints Editor
Information about Timing Constraints Editor
13 SmartTime Static Timing Analyzer
Information about SmartTime Static Timing Analyzer
14 SmartPower
Information about SmartPower
15 Programming and Debugging
Information about Programming and Debugging
16 Macro Library
Information about Macro Library for SmartFusion2, IGLOO2 and PolarFire
17 Custom Flow
Information about Custom Flow
18 Design Separation Methodology
Information about Design Separation Methodology
19 Microchip Separation Verification Tool
Information about Microchip Separation Verification Tool
20 PolarFire SoC Microcontroller Subsystem (MSS)
Information about PolarFire SoC Microcontroller Subsystem (MSS)
21 Tcl Command Reference
Information about Tcl Command Reference
22 More Information
Additional information about other Microchip products
23 Technical Support
24 About Microchip
More information about Microchip

3.5.1.16.3 ECC Support Status

(Ask a Question)

The following is a summary of supported features and limitations in the current release:

If you use an ECC memory, SmartHLS will always instantiate an LSRAM block. uSRAM blocks with ECC (only available for RTG4™ devices) are currently not supported (Planned for future releases).
Only non-pipelined ECC mode is supported (Pipelined ECC is planned for future releases).
Byte-write enable memories with ECC (only available for PolarFire® devices) are not supported (Planned for future releases).
SmartHLS FIFOs/Data buffers IPs do not support ECC (Planned for future releases).
Only local ECC memories instantiated by SmartHLS are supported (External ECC memories are planned for future releases).
ECC with memory controllers are not supported in current release (Planned for future releases).
If memory is partitioned into individual elements (registers), ECC logic will be optimized away.
Memory initialization for RTG4™ devices need to be configured manually. For more details, see AN4892: RTG4 SRAM Initialization After Powerup Using μPROM Application Note.