3.5.1.16.2 Error Emulation
(Ask a Question)The ECC memory simulation models can emulate errors by randomly asserting the ECC signals based on a user-defined probability. For more details on SRAM ECC emulation, see Table 4-9. Vsim Command Options in Libero® SoC Design Flow User Guide. SmartHLS™ provides Tcl commands to emulate the errors in both software and hardware:
ECC_ERROR_PROBABILITY- A value between 0.0 and 1.0 that represents the error probability (single or double-bit errors) in software and simulation.
ECC_CORRECTION_PROBABILITY- A value between 0.0 and 1.0 that represents the probability of a single-bit error when an error is detected in software and simulation.
ECC_WARNING_MSGS_ON- Enable messages from the memory RTL model when an error is detected.
For more details and examples of the above Tcl commands, check out 3.6.2.4.29 ECC_ERROR_PROBABILITY, 3.6.2.4.30 ECC_CORRECTION_PROBABILITY, and 3.6.2.4.31 ECC_WARNING_MSGS_ON in Constraints Manual.
Warning: Due to using a random function to emulate the error/correction behavior, the error location and number of errors/corrections can be different between software and simulation.