3.5.1.20.1 Module Control Interface

The top-level Verilog module generated by SmartHLS™ is always associated with a module control interface to start the HLS module, read completion status and retrieve return data. Two interface protocols are available for module control, simple and axi_target. The default interface is simple. The module control interface can be explicitly specified via an interface pragma at the beginning of the top-level function's definition body:

// Add at the beginning of the function definition
#pragma HLS interface control type(<simple|axi_target>)