3.5.1.18.3 Error Simulation
(Ask a Question)Important: ECC error simulation support is an alpha feature in SmartHLS™, and is under active development. ECC error injection feature is not supported for external memories, FIFOs and Line Buffers in this release.
SmartHLS supports ECC error simulation for RTG4 LSRAM, where error can be injected to a specific address based on user provided address and data mask bits. ECC flags will be asserted depending on the data mask bits. For more information on RTG4 LSRAM error simulation, refer to the Verilog Task-Based Flag Assertion and Simulation Flow Example sections of the RTG4 Fabric User Guide.
See Inject ECC Error for Error Simulation inError Correction Code (ECC) Library for information about the C++ API for ECC error injection in both software and hardware.
Important: To use ECC error simulation, probability-based error emulation must be disabled.