Memory Usage
(Ask a Question)The memory usage section lists the memories used by the generated circuit, grouped by the type of memory architecture. Please refer to Memory Architecture section for more details about the memory architecture used by SmartHLS™.
+-------------------------------------------------------------------------------------------------------------------------+ | Local Constant Memories | +-------+--------------------------------------------------------+------+-------------+------------+-------+--------------+ | Name | Accessing Function(s) | Type | Size [Bits] | Data Width | Depth | Read Latency | +-------+--------------------------------------------------------+------+-------------+------------+-------+--------------+ | gauss | blackscholes_hw (concurrent access through an arbiter) | ROM | 8192 | 32 | 256 | 1 | +-------+--------------------------------------------------------+------+-------------+------------+-------+--------------+ +---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Shared Local Memories | +-------------+-------------------------------------------------------------------------------------+---------------+-------------+------------+-------+--------------+ | Name | Accessing Function(s) | Type | Size [Bits] | Data Width | Depth | Read Latency | +-------------+-------------------------------------------------------------------------------------+---------------+-------------+------------+-------+--------------+ | bdata_0 | blackscholes_hw, option_pricing (concurrent access through an arbiter) | Register | 32 | 32 | 1 | 0 | | bdata_1 | blackscholes_hw, option_pricing (concurrent access through an arbiter) | Register | 32 | 32 | 1 | 0 | | idata_0 | mersenne_twister_init_hw, option_pricing (concurrent access through an arbiter) | Register | 1 | 1 | 1 | 0 | | idata_1 | mersenne_twister_init_hw, option_pricing (concurrent access through an arbiter) | Register | 32 | 32 | 1 | 0 | | init_fifo | mersenne_twister_generate_hw, mersenne_twister_init_hw | FIFO (LUTRAM) | 64 | 32 | 2 | 1 | | random_fifo | blackscholes_hw, mersenne_twister_generate_hw | FIFO (LUTRAM) | 64 | 32 | 2 | 1 | | tdata_0 | mersenne_twister_generate_hw, option_pricing (concurrent access through an arbiter) | Register | 32 | 32 | 1 | 0 | | tdata_1 | mersenne_twister_generate_hw, option_pricing (concurrent access through an arbiter) | Register | 32 | 32 | 1 | 0 | +-------------+-------------------------------------------------------------------------------------+---------------+-------------+------------+-------+--------------+ +-------------------------------------------------------------------------------------------------------------------------------+ | Aliased Memories | +------------------------+---------------------+-----------------------+------+-------------+------------+-------+--------------+ | Name | Memory Controller | Accessing Function(s) | Type | Size [Bits] | Data Width | Depth | Read Latency | +------------------------+---------------------+-----------------------+------+-------------+------------+-------+--------------+ | foo_entry_local_array1 | memory_controller_0 | foo, foo_sub | RAM | 160 | 32 | 5 | 1 | | foo_entry_local_array2 | memory_controller_0 | foo, foo_sub | RAM | 160 | 32 | 5 | 1 | +------------------------+---------------------+-----------------------+------+-------------+------------+-------+--------------+ +---------------------------------------------------------------------------------------------------------+ | I/O Memories | +--------+-----------------------+----------------------+-------------+------------+-------+--------------+ | Name | Accessing Function(s) | Type | Size [Bits] | Data Width | Depth | Read Latency | +--------+-----------------------+----------------------+-------------+------------+-------+--------------+ | rd_arr | kernel | ROM | undef | 16 | undef | 1 | | rd_reg | kernel | Register (Read-Only) | undef | 16 | undef | 0 | | wr_arr | kernel | RAM | undef | 16 | undef | 1 | | wr_reg | kernel | Register | undef | 16 | undef | 0 | +--------+-----------------------+----------------------+-------------+------------+-------+--------------+
The example tables above show the accessing functions and the hardware implementation of each "memory" in the software.
- The Type column shows how a memory is implemented in hardware, which could be in RAM, ROM (read-only), register or FIFO (only applicable to
hls::FIFOtype variables in C++). - The Size column reports the total size of the memory in bits, equals to Data Width * Depth.
- The Data Width refers to the bit-width of the data ports of a RAM/FIFO, or the bit-width of a register.
- The Depth field represents the depth of a RAM or FIFO, and it is always 1 for register.
- Aliased Memories have an additional column showing the name of the Memory Controller of which the memory is being placed behind. So you can see which memories are aliasing and being put behind the same memory controller to support aliased memory accesses.
- I/O Memories have Size and Depth to be undef. This is because I/O interface memories are not instantiated inside the SmartHLS-generated circuit.