38.13.26 CxFIFOUAy
Note:
- The individual bytes in this
multibyte register can be accessed with the following register names:
- CxFIFOCONyT: Accesses the top byte FIFOCONy[31:24]
- CxFIFOCONyU: Accesses the upper byte FIFOCONy[23:16]
- CxFIFOCONyH: Accesses the high byte FIFOCONy[15:8]
- CxFIFOCONyL: Accesses the low byte FIFOCONy[7:0]
- [y] denotes FIFO number, from 1 to 3.
- This register is not ensured to read correctly in Configuration mode and may only be accessed when the module is not in Configuration mode.
| Name: | CxFIFOUAy |
| Address: | 0x00 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| FIFOUA[31:24] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | x | x | x | x | x | x | x | x | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| FIFOUA[23:16] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | x | x | x | x | x | x | x | x | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| FIFOUA[15:8] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | x | x | x | x | x | x | x | x | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FIFOUA[7:0] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | x | x | x | x | x | x | x | x | |
Bits 31:0 – FIFOUA[31:0] FIFO User Address bits
| Name | Description |
|---|---|
TXEN = 1 (FIFO configured as
transmit buffer |
A read of this register will return the address where the next message is to be written (FIFO head) |
TXEN = 0 (FIFO configured as
receive buffer |
A read of the register will return the address where the next message is to be read (FIFO tail) |