38.13.4 CxTDC

CAN Transmitter Delay Compensation Register

Note:

The individual bytes in this multibyte register can be accessed with the following register names:
- CxTDCT: Accesses the top byte TDC[31:24]
- CxTDCU: Accesses the upper byte TDC[23:16]
- CxTDCH: Accesses the high byte TDC[15:8]
- CxTDCL: Accesses the low byte TDC[7:0]
This register can only be modified in Configuration mode (OPMOD[2:0] = 100).

Name:	CxTDC
Address:	0x010C


Bit	31	30	29	28	27	26	25	24
							EDGFLTEN	SID11EN
Access							R/W	R/W
Reset							0	0


Bit	23	22	21	20	19	18	17	16
							TDCMOD[1:0]
Access							R/W	R/W
Reset							1	0


Bit	15	14	13	12	11	10	9	8
		TDCO[6:0]
Access		R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset		0	0	1	0	0	0	0


Bit	7	6	5	4	3	2	1	0
			TDCV[5:0]
Access			R/W	R/W	R/W	R/W	R/W	R/W
Reset			0	0	0	0	0	0

Bit 25 – EDGFLTEN Enable Edge Filtering During Bus Integration State

Value	Description
1	Edge filtering is enabled according to ISO11898-1:2015
0	Edge filtering is disabled

Bit 24 – SID11EN Enable 12-Bit SID in CAN FD Base Format Messages

Value	Description
1	RRS is used as SID11 in CAN FD base format messages: SID[11:0]={SID[10:0],SID11}
0	Does not use RRS; SID[10:0]

Bits 17:16 – TDCMOD[1:0] Transmitter Delay Compensation Mode (Secondary Sample Point (SSP))

Value	Description
11-10	Auto: Measures delay and adds TSEG1[4:0] (CxDBTCFG[19:16]; adds TDCO[6:0]
01	Manual: Does not measure, uses TDCV[5:0] +TDCO[6:0]
00	Disables

Bits 14:8 – TDCO[6:0] Transmitter Delay Compensation Offset (Secondary Sample Point (SSP))

Value is two’s complement, offset can be positive, zero or negative

Value	Description
0111111	63 x T_CY
0000000	0 x T_CY
11111111	-64 x T_CY

Bits 5:0 – TDCV[5:0] Transmitter Delay Compensation Value bits (Secondary Sample Point (SSP))

Value	Description
111111	63 x T_CY
000000	0 x T_CY

The individual bytes in this multibyte register can be accessed with the following register names: CxTDCT: Accesses the top byte TDC[31:24] CxTDCU: Accesses the upper byte TDC[23:16] CxTDCH: Accesses the high byte TDC[15:8] CxTDCL: Accesses the low byte TDC[7:0] This register can only be modified in Configuration mode (OPMOD[2:0] = 100).