36.15 TWI

Figure 36-6. TWI - Timing Requirements

Table 36-21. TWI - Timing Specifications
Symbol	Description	Min.	Typ.✝	Max.	Unit	Condition
f_SCL	SCL clock frequency	—	—	1000	kHz	Max. frequency requires system clock over 12 MHz
V_HYS	Hysteresis of Schmitt Trigger inputs	0.05 × V_DD	—	0.4 × V_DD	V
V_OL	Output low voltage	—	—	0.4V	V	I_load = 3 mA, V_DD > 2V
V_OL	Output low voltage	—	—	0.2 × V_DD	V	I_load = 2 mA, V_DD ≤ 2V
I_OL	Low-level output current	3	—	—	mA	V_OL = 0.4V, V_DD > 2
I_OL	Low-level output current	2	—	—	mA	0.2 × V_DD, V_DD ≤ 2V
t_SP *	Spikes suppressed by the input filter	0	—	50	ns
t_{HD_STA} *	Hold time (repeated) Start condition	4.0	—	—	µs	f_SCL ≤ 100 kHz
		0.6	—	—		f_SCL ≤ 400 kHz
		0.26	—	—		f_SCL ≤ 1 MHz
T_LOW *	Low period of SCL Clock	4.7	—	—	µs	f_SCL ≤ 100 kHz
		0.6	—	—		f_SCL ≤ 400 kHz
		0.35	—	—		f_SCL ≤ 1 MHz
T_HIGH *	High period of SCL Clock	4.0	—	—	µs	f_SCL ≤ 100 kHz
		0.6	—	—		f_SCL ≤ 400 kHz
		0.26	—	—		f_SCL ≤ 1 MHz
t_{SU_STA} *	Setup time for a repeated Start condition	4.7	—	—	µs	f_SCL ≤ 100 kHz
		0.6	—	—		f_SCL ≤ 400 kHz
		0.26	—	—		f_SCL ≤ 1 MHz
t_{HD_DAT} *	Data hold time	—	0	—	ns	SDAHOLD[1:0] = `0x0`
t_{HD_DAT} *	Data hold time	300	—	900	ns	SDAHOLD[1:0] = `0x3`
t_{SU_DAT} *	Data setup time	250	—	—	ns	f_SCL ≤ 100 kHz
		100	—	—		f_SCL ≤ 400 kHz
		50	—	—		f_SCL ≤ 1 MHz
t_{SU_STO} *	Setup time for Stop condition	4	—	—	µs	f_SCL ≤ 100 kHz
		0.6	—	—		f_SCL ≤ 400 kHz
		0.26	—	—		f_SCL ≤ 1 MHz
t_BUF *	Bus free time between a Stop and Start condition	4.7	—	—	µs	f_SCL ≤ 100 kHz
t_BUF *	Bus free time between a Stop and Start condition	1.3	—	—	µs	f_SCL ≤ 400 kHz
t_CS	Client Clock Stretching delay	—	—	250	ns
✝ Unless otherwise specified, data in the “Typ.” column is at T_A = 25°C and V_DD = 3.0V . These parameters are not tested and are for design guidance only. * These parameters are not tested and are for design guidance only.