36.18 UPDI

Figure 36-7. UPDI Enable Sequence with Dedicated UPDI Pin

Table 36-27. UPDI Timing Specifications
Symbol	Description	Min.	Max.	Unit	Conditions
t_RES *	Duration of Handshake/Break on RESET	10	200	µs
t_UPDI *	Duration of UPDI.txd = 0	10	200	µs
t_Deb0 *	Duration of Debugger.txd = 0	0.2	1	µs
t_DebZ *	Duration of Debugger.txd = z	200	14000	µs
f_UPDI *	UPDI clock frequency	—	4	MHz	1.8V ≤ V_DD ≤ 5.5V T_A < 0ºC or T_A > +50ºC
		—	8		1.8V ≤ V_DD ≤ 5.5V 0ºC ≤ T_A ≤ +50ºC
		—	8		2.7V ≤ V_DD ≤ 5.5V T_A < 0ºC or T_A > +50ºC
		—	16		2.7V ≤ V_DD ≤ 5.5V 0ºC ≤ T_A ≤ +50ºC
		—	16		4.5V ≤ V_DD ≤ 5.5V T_A < 0ºC or T_A > +50ºC
		—	32		4.5V ≤ V_DD ≤ 5.5V 0ºC ≤ T_A ≤ +50ºC
* These parameters are characterized but not tested in production.

Figure 36-8. UPDI Enable Sequence by High-Voltage (HV) Programming

Table 36-28. UPDI HV Pulse Specifications
Symbol	Description	Min.	Typ.	Max.	Unit	Conditions
V_HV *	Debugger RESET HV signal level	V_DD+2	7.5	8.5	V	Never exceed the abs. max. ratings of the RESET pin
T_HV **	Debugger RESET HV signal duration	10			µs
T_{UPDI_TIMEOUT} *	Time to receive valid key after HV pulse		65		ms
* These parameters are characterized but not tested in production. ** These parameters are for design guidance only and are not tested.