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SmartTime Static Timing Analyzer (STA) User Guide Libero® SoC v2022.2

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8 Generating Timing Reports
8.3 Understanding Timing Reports
8.3.6 External Recovery Set

Libero® SoC v2022.2

Introduction
1 About SmartTime
2 Design Flows with SmartTime
3 Starting and Closing SmartTime
4 Configuring SmartTime Settings
5 SmartTime Toolbar
6 SmartTime Timing Analyzer
7 Advanced Timing Analysis
8 Generating Timing Reports
- 8.1 Types of Reports
- 8.2 Generating a Timing Report
  The Timing Report allows you to determine whether timing problems exist in your design.
- 8.3 Understanding Timing Reports
- 8.4 Generating a Timing Violation Report
  The Timing Violations Report provides a Flat Slack Report centered around constraint violations.
- 8.5 Understanding Timing Violation Reports
- 8.6 Generating a Constraints Coverage Report
  The Constraints Coverage Report contains information about the constraints in the design.
- 8.7 Understanding Constraints Coverage Reports
- 8.8 Generating a Bottleneck Report
- 8.9 Understanding Bottleneck Reports - SmartFusion2, IGLOO2, RTG4, and PolarFire
- 8.10 Generating a Datasheet Report
  The Datasheet Report shows information about a design’s external characteristics.
- 8.11 Understanding Datasheet Reports
- 8.12 Generating a Combinational Loop Report
  The Combinational Loop Report shows all loops found during initialization and reports pins associated with the loop(s) and the location where a loop is broken.
- 8.13 Understanding Combinational Loop Reports
- 8.14 Generating a Clock Domain Crossing (CDC) Report
  The Clock Domain Crossing (CDC) Report analyzes timing paths that cross from one clock domain (the source clock) to another clock domain (the destination clock). The CDC report helps identify instances where there may be data loss or metastability issues.
9 Timing Concepts
10 SmartTime Tutorials
11 SmartTime Dialog Boxes
12 Tcl Commands
13 Glossary
14 Revision History
Microchip FPGA Support
Microchip Information

8.3.6 External Recovery Set

This set reports the external recovery check timing for asynchronous control signals, such as asynchronous set/reset.

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