23.9.7 I2C Configuration

The CFGI2C dictates the peripheral clock selection described in the Clock and Reset Unit chapter. See Clock and Reset Unit (CRU) from Related Links.

Name: CFGI2C
Offset: 0x70
Reset: 0x00000000
Property: -

Bit 3130292827262524 
  SLRTEN6   SLRTEN2SLRTEN1SLRTEN0 
Access R/W/LR/W/LR/W/LR/W/L 
Reset 0000 
Bit 2322212019181716 
  SLRCTRL6   SLRCTRL2SLRCTRL1SLRCTRL0 
Access R/W/LR/W/LR/W/LR/W/L 
Reset 0000 
Bit 15141312111098 
  I2CDSEL6   I2CDSEL2I2CDSEL1I2CDSEL0 
Access R/W/LR/W/LR/W/LR/W/L 
Reset 0000 
Bit 76543210 
  SMBUSEN6   SMBUSEN2SMBUSEN1SMBUSEN0 
Access R/W/LR/W/LR/W/LR/W/L 
Reset 0000 

Bit 30 – SLRTEN6 I2C Slew Rate Enable for SERCOM6

Note:
  • This field is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
0 I2C Slew Rate is disabled
1 I2C Slew Rate is enabled

Bit 26 – SLRTEN2 I2C Slew Rate Enable for SERCOM2

Note:
  • This field is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
0 I2C Slew Rate is disabled
1 I2C Slew Rate is enabled

Bit 25 – SLRTEN1 I2C Slew Rate Enable for SERCOM1

Note:
  • This field is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
0 I2C Slew Rate is disabled
1 I2C Slew Rate is enabled

Bit 24 – SLRTEN0 I2C Slew Rate Enable for SERCOM0

Note:
  • This field is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
0 I2C Slew Rate is disabled
1 I2C Slew Rate is enabled

Bit 22 – SLRCTRL6 Slew Rate Control for SERCOM6

Note:
  • This field is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
0 Slew Rate Control is controlled via GPIO registers
1 Slew Rate Control is controlled via SERCOM registers

Bit 18 – SLRCTRL2 Slew Rate Control for SERCOM2

Note:
  • This field is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
0 Slew Rate Control is controlled via GPIO registers
1 Slew Rate Control is controlled via SERCOM registers

Bit 17 – SLRCTRL1 Slew Rate Control for SERCOM1

Note:
  • This field is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
0 Slew Rate Control is controlled via GPIO registers
1 Slew Rate Control is controlled via SERCOM registers

Bit 16 – SLRCTRL0 Slew Rate Control for SERCOM0

Note:
  • This field is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
0 Slew Rate Control is controlled via GPIO registers
1 Slew Rate Control is controlled via SERCOM registers

Bit 14 – I2CDSEL6 I2C Delay Select for SERCOM6

Note:
  • This field is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
0 I2C delay is disabled
1 I2C delay is enabled

Bit 10 – I2CDSEL2 I2C Delay Select for SERCOM2

Note:
  • This field is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
0 I2C delay is disabled
1 I2C delay is enabled

Bit 9 – I2CDSEL1 I2C Delay Select for SERCOM1

Note:
  • This field is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
0 I2C delay is disabled
1 I2C delay is enabled

Bit 8 – I2CDSEL0 I2C Delay Select for SERCOM0

Note:
  • This field is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
0 I2C delay is disabled
1 I2C delay is enabled

Bit 6 – SMBUSEN6 SMBus Enable for SERCOM6

Note:
  • This field is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
0 SMBus is disabled
1 SMBus is enabled

Bit 2 – SMBUSEN2 SMBus Enable for SERCOM2

Note:
  • This field is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
0 SMBus is disabled
1 SMBus is enabled

Bit 1 – SMBUSEN1 SMBus Enable for SERCOM1

Note:
  • This field is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
0 SMBus is disabled
1 SMBus is enabled

Bit 0 – SMBUSEN0 SMBus Enable for SERCOM0

Note:
  • This field is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
0 SMBus is disabled
1 SMBus is enabled