23.9.8 Peripheral Clock Generator 1
The CFGPCLKGEN1 dictates the peripheral clock selection described in the Clock and Reset Unit chapter. See Clock and Reset Unit (CRU) from Related Links.
There is no Flash location for this register because the purpose of this register is to provide application-based peripheral clocking selection. This is best handled in the application software drivers.
| Name: | CFGPCLKGEN1 |
| Offset: | 0x80 |
| Reset: | 0x00000000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| CM4TCD | CM4TCSEL[2:0] | SERCOM345CD | SERCOM345CSEL[2:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| TCC12CD | TCC12CSEL[2:0] | SERCOM6CD | SERCOM6CSEL[2:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SERCOM012CD | SERCOM012CSEL[2:0] | FREQMMCD | FREQMMCSEL[2:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FREQMRCD | FREQMRCSEL[2:0] | EICCD | EICCSEL[2:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 31 – CM4TCD CM4_Trace Peripheral Clock Disable
Note: This field is only writable when CFGCON0.PGLOCK is ‘
0’.| Value | Description |
|---|---|
| 0 | Clock is disabled |
| 1 | Clock is enabled |
Bits 30:28 – CM4TCSEL[2:0] CM4_Trace Peripheral Clock Selection
Note: This field is only writable when CFGCON0.PGLOCK is ‘
0’.| Value | Description |
|---|---|
| 0 | No clock is selected |
| 1-6 | REFO1-6 clock is selected |
| 7 | Low power clock is selected |
Bit 27 – SERCOM345CD SERCOM3, SERCOM4 and SERCOM5 Peripheral Clock Disable
Note: This field is only writable when CFGCON0.PGLOCK is
‘
0’.| Value | Description |
|---|---|
| 0 | Clock is disabled |
| 1 | Clock is enabled |
Bits 26:24 – SERCOM345CSEL[2:0] SERCOM3, SERCOM4 and SERCOM5 Peripheral Clock Selection
Note: This field is only writable when CFGCON0.PGLOCK is
‘
0’.| Value | Description |
|---|---|
| 0 | No clock is selected |
| 1-6 | REFO1-6 clock is selected |
| 7 | Low power clock is selected |
Bit 23 – TCC12CD TCC1 and TCC2 Peripheral Clock Disable
Note: This field is only writable when CFGCON0.PGLOCK is ‘
0’.| Value | Description |
|---|---|
| 0 | Clock is disabled |
| 1 | Clock is enabled |
Bits 22:20 – TCC12CSEL[2:0] TCC1 and TCC2 Peripheral Clock Selection
Note: This field is only writable when CFGCON0.PGLOCK is ‘
0’.| Value | Description |
|---|---|
| 0 | No clock is selected |
| 1-6 | REFO1-6 clock is selected |
| 7 | Low power clock is selected |
Bit 19 – SERCOM6CD SERCOM6 Peripheral Clock Disable
Note: This field is only writable when CFGCON0.PGLOCK is
‘
0’.| Value | Description |
|---|---|
| 0 | Clock is disabled |
| 1 | Clock is enabled |
Bits 18:16 – SERCOM6CSEL[2:0] SERCOM6 Peripheral Clock Selection
Note: This field is only writable when CFGCON0.PGLOCK is
‘
0’.| Value | Description |
|---|---|
| 0 | No clock is selected |
| 1-6 | REFO1-6 clock is selected |
| 7 | Low power clock is selected |
Bit 15 – SERCOM012CD SERCOM0, SERCOM1 and SERCOM2 Peripheral Clock Disable
Note: This field is only writable when CFGCON0.PGLOCK is ‘
0’.| Value | Description |
|---|---|
| 0 | Clock is disabled |
| 1 | Clock is enabled |
Bits 14:12 – SERCOM012CSEL[2:0] SERCOM0, SERCOM1 and SERCOM2 Peripheral Clock Selection
Note: This field is only writable when CFGCON0.PGLOCK is ‘
0’.| Value | Description |
|---|---|
| 0 | No clock is selected |
| 1-6 | REFO1-6 clock is selected |
| 7 | Low power clock is selected |
Bit 11 – FREQMMCD FREQM Measurement Clock Disable
Note: This field is only writable when CFGCON0.PGLOCK is ‘
0’.| Value | Description |
|---|---|
| 0 | Clock is disabled |
| 1 | Clock is enabled |
Bits 10:8 – FREQMMCSEL[2:0] FREQM Measurement Clock Selection
Note: This field is only writable when CFGCON0.PGLOCK is ‘
0’.| Value | Description |
|---|---|
| 0 | No clock is selected |
| 1-6 | REFO1-6 clock is selected |
| 7 | Low power clock is selected |
Bit 7 – FREQMRCD FREQM Reference Clock Disable
Note: This field is only writable when CFGCON0.PGLOCK is ‘
0’.| Value | Description |
|---|---|
| 0 | Clock is disabled |
| 1 | Clock is enabled |
Bits 6:4 – FREQMRCSEL[2:0] FREQM Reference Clock Selection
Note: This field is only writable when CFGCON0.PGLOCK is ‘
0’.| Value | Description |
|---|---|
| 0 | No clock is selected |
| 1-6 | REFO1-6 clock is selected |
| 7 | Low power clock is selected |
Bit 3 – EICCD EIC Peripheral Clock Disable
Note: This field is only writable when CFGCON0.PGLOCK is ‘
0’.| Value | Description |
|---|---|
| 0 | Clock is disabled |
| 1 | Clock is enabled |
Bits 2:0 – EICCSEL[2:0] EIC Peripheral Clock Selection
Note: This field is only writable when CFGCON0.PGLOCK is ‘
0’.| Value | Description |
|---|---|
| 0 | No clock is selected |
| 1-6 | REFO1-6 clock is selected |
| 7 | Low power clock is selected |