23.9.3 Configuration Control Register 2

This register is loaded with trusted data from FBCFG3/DEVCFG2 during the pre-boot period.

Trusted data from Flash is the configuration word reading from Flash memory which does not receive a BCFG fail status and BINFOVALID = 0. If accompanied by fail status BCFGFAIL (RCON[26]) or blank/erase indication, Reset values (described in the following register description) are retained and new values from FBCFG3 are not loaded.

Under all conditions, Flash loading is omitted for POSCMD[1:0] bits in CFGCON2 register. Hence, writing these bits in Boot Flash must not have an effect on the configuration register.

Name: CFGCON2(L)
Offset: 0x20
Reset: 0x7f7fff38
Property: -

Bit 3130292827262524 
 DMTENDMTCNT[4:0]WINSZ[1:0] 
Access R/W/LR/W/LR/W/LR/W/LR/W/LR/W/LR/W/LR/W/L 
Reset 01111111 
Bit 2322212019181716 
 WDTENWINDISWDTSPGMWDTPSR[4:0] 
Access R/W/LR/W/LR/W/LR/W/LR/W/LR/W/LR/W/LR/W/L 
Reset 01111111 
Bit 15141312111098 
 FSCMENCKSWENWAKE2SPDSOSCSELWDTRMCS[1:0]POSCMD[1:0] 
Access R/W/LR/W/LR/W/LR/W/LR/W/LR/W/LR/W/LR/W/L 
Reset 11111111 
Bit 76543210 
 PMUTEST_VDD_EN DMTINTV[2:0]ACMP_CYCLE[2:0] 
Access R/W/LR/W/LR/W/LR/W/LR/W/LR/W/LR/W/L 
Reset 0111000 

Bit 31 – DMTEN Dead Man Timer Enable

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1DMT is enabled always and DMTCON.ON bit does not have control
0DMT disabled (control is placed on the DMTCON.ON bit)

Bits 30:26 – DMTCNT[4:0] Dead Man Timer Count Select

Note: These bits are only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
00000Counter value is 2^8 for DMTPSCNT[31:0]
00001Counter value is 2^9 for DMTPSCNT[31:0]
......
10100Counter value is 2^28 for DMTPSCNT[31:0]
10101Counter value is 2^29 for DMTPSCNT[31:0]
10110Counter value is 2^30 for DMTPSCNT[31:0]
10111Counter value is 2^31 for DMTPSCNT[31:0]
11000 - 11111Reserved

Bits 25:24 – WINSZ[1:0] Watchdog Timer Window Size

Note: These bits are only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
00Window size is 75%
01Window size is 50%
10Window size is 37.5%
11Window size is 25%

Bit 23 – WDTEN Watchdog Timer Enable

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1WDT is enabled always and WDTCON.ON bit does not have control
0WDT is disabled (control is placed on the WDTCON.ON bit)

Bit 22 – WINDIS Windowed Watchdog Timer Disable

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1Standard WDT selected; windowed WDT disabled
0Windowed WDT enabled

Bit 21 – WDTSPGM Watchdog Timer Stop during Flash Programming

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1The WDT stops during NVR programming
0The WDT runs during NVR programming

Bits 20:16 – WDTPSR[4:0] Watchdog Timer Post-scale Select Run bits

Note: These bits are only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
101001:1048576
100111:524288
100101:262144
100011:131072
100001:65536
011111:32768
011101:16384
011011:8192
011001:4096
010111:2048
010101:1024
010011:512
010001:256
001111:128
001101:64
001011:32
001001:16
000111:8
000101:4
000011:2
000001:1

Bit 15 – FSCMEN Fail-Safe Clock Monitor Enable

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1FSCM enabled
0FSCM disabled

Bit 14 – CKSWEN Software Clock Switching Enable

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1Software clock switching enabled
0Software clock switching disabled

Bit 13 – WAKE2SPD Two-Speed Start-up Enabled in the Sleep mode

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1When the device EXITS Sleep mode, the SYS_CLK is from FRC until the selected clock is ready.
0Not applicable.

Bit 12 – SOSCSEL SOSC Selection Configuration

Note: This bit is only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1Crystal (SOSCI/SOSCO) mode
0Digital (SCLKI) mode

Bits 11:10 – WDTRMCS[1:0] WDT RUN Mode Clock Select

Note: These bits are only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
11LPRC
10Reserved
01Reserved
00WDT PB Clock (PB1_CLK)

Bits 9:8 – POSCMD[1:0] Primary Oscillator Configuration

Note: These bits are only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
11Primary Oscillator mode is disabled
10Reserved
01Reserved
00Primary Oscillator mode is selected

Bit 7 – PMUTEST_VDD_EN PMU Test Output or VDD/2 Enable via ADC IE12

Note: These bits are only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
1PMU Test output monitor is enabled
0VDD/2 Monitor is enabled

Bits 5:3 – DMTINTV[2:0] Dead Man Timer Count Window Interval

Note: These bits are only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
000Window/Interval value is zero for DMTPSINTV[31:0] - Windowed mode is disabled
001Window/Interval value is 1/2 Counter value for DMTPSINTV[31:0]
010Window/Interval value is 3/4 Counter value for DMTPSINTV[31:0]
011Window/Interval value is 7/8 Counter value for DMTPSINTV[31:0]
100Window/Interval value is 15/16 Counter value for DMTPSINTV[31:0]
101Window/Interval value is 31/32 Counter value for DMTPSINTV[31:0]
110Window/Interval value is 63/64 Counter value for DMTPSINTV[31:0]
111Window/Interval value is 127/128 Counter value for DMTPSINTV[31:0]

Bits 2:0 – ACMP_CYCLE[2:0] AC Comparator Result Wait Cycles

Note: These bits are only writable when CFGLOCK[1:0] is ‘00’.
ValueDescription
nWait for 32 µs* ACMP_CYCLE[2:0]+1 cycles to generate comparator done indication