23.9.2 Configuration Control Register 1
This register is loaded with trusted data from FBCFG2/DEVCFG1 during the pre-boot period.
Trusted data from Flash is the configuration word reading from Flash memory which does not receive BCFG fail status and BINFOVALID = 0. If accompanied by fail status BCFGFAIL (RCON[26]) or blank/erase indication, Reset values (described in the following register description) are retained, and new values from FBCFG2 are not loaded.
Under all conditions, Flash loading is omitted for the ZBTWKSYS bit in CFGCON1 register. Hence, writing this bit in Boot Flash will not have an effect on the configuration register.
| Name: | CFGCON1(L) |
| Offset: | 0x10 |
| Reset: | 0x1f00403B |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| CAN1_PIN_EN | CLKZBREF | QSPIDDRM | WDTPSS[4:0] | ||||||
| Access | R/W/L | R/W/L | R/W/L | R/W/L | R/W/L | R/W/L | R/W/L | R/W/L | |
| Reset | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| USBDPRTRIM[1:0] | USBDPFTRIM[1:0] | USBDMRTRIM[1:0] | USBDMFTRIM[1:0] | ||||||
| Access | R/W/L | R/W/L | R/W/L | R/W/L | R/W/L | R/W/L | R/W/L | R/W/L | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| QSCHE_EN | SMCLR | SERCOM_HSEN[2:0] | QSPI_HSEN | CMP1_OE | CMP0_OE | ||||
| Access | R/W/L | R/W/L | R/W/L | R/W/L | R/W/L | R/W/L | R/W/L | R/W/L | |
| Reset | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ZBTWKSYS | CCL_OE | TRCEN | CAN0_PIN_EN | ||||||
| Access | R/W/L | R/W/L | R/W/L | R/W/L | |||||
| Reset | 0 | 0 | 1 | 0 |
Bit 31 – CAN1_PIN_EN CAN1 Pin Enable
Note: This bit is only writable when
CFGLOCK[1:0] is ‘
00’.| Value | Description |
|---|---|
| 1 | CAN1 pins are enabled |
| 0 | CAN1 pins are disabled |
Bit 30 – CLKZBREF External Reference Clock ZB Enable
The external reference clock output from the 802.15.4 wireless subsystem on the REFO1 pin, which is configurable through PPS
Note: This bit is only writable when CFGLOCK[1:0] is ‘
00’.| Value | Description |
|---|---|
| 1 | Enable clk_zb_to_ext on PPS.REFO1 |
| 0 | No clk_zb_to_ext on PPS.REFO1, PPS.REFO1 remains unchanged |
Bit 29 – QSPIDDRM QSPI Double Data Rate (DDR) Mode Clock Enable
Note:
- When using the QSPI DDR mode, the System Clock (SYS_CLK) must be <= 32 MHz.
- This bit is only writable when CFGLOCK[1:0] is ‘
00’.
| Value | Description |
|---|---|
| 1 | QSPI DDR mode clock is enabled |
| 0 | QSPI DDR mode clock is disabled |
Bits 28:24 – WDTPSS[4:0] Watchdog Timer Post-scale Select Sleep bits
Note: These bits are only writable when CFGLOCK[1:0] is ‘
00’.| Value | Description |
|---|---|
| 10100 | 1:1048576 |
| 10011 | 1:524288 |
| 10010 | 1:262144 |
| 10001 | 1:131072 |
| 10000 | 1:65536 |
| 01111 | 1:32768 |
| 01110 | 1:16384 |
| 01101 | 1:8192 |
| 01100 | 1:4096 |
| 01011 | 1:2048 |
| 01010 | 1:1024 |
| 01001 | 1:512 |
| 01000 | 1:256 |
| 00111 | 1:128 |
| 00110 | 1:64 |
| 00101 | 1:32 |
| 00100 | 1:16 |
| 00011 | 1:8 |
| 00010 | 1:4 |
| 00001 | 1:2 |
| 00000 | 1:1 |
Bits 23:22 – USBDPRTRIM[1:0] USB DP Rise Trim fuse bits
Note: This bit is only writable when CFGLOCK[1:0] is ‘
00’.Bits 21:20 – USBDPFTRIM[1:0] USB DP Fall Trim fuse bits
Note: This bit is only writable when CFGLOCK[1:0] is ‘
00’.Bits 19:18 – USBDMRTRIM[1:0] USB DM Rise Trim fuse bits
Note: This bit is only writable when CFGLOCK[1:0] is ‘
00’.Bits 17:16 – USBDMFTRIM[1:0] USB DM Fall Trim fuse bits
Note: This bit is only writable when CFGLOCK[1:0] is ‘
00’.Bit 15 – QSCHE_EN QSPI Address Space Cache Attribute
Note: This bit is only writable when CFGLOCK[1:0] is ‘
00’.| Value | Description |
|---|---|
| 1 | Cache attribute is enabled |
| 0 | Caching is disabled |
Bit 14 – SMCLR Selects CRU handling of NMCLR Control
Note: This bit is only writable when CFGLOCK[1:0] is ‘
00’.| Value | Description |
|---|---|
| 1 | Does not reset all device NMCLR Reset states |
| 0 | NMCLR external Reset causes a faux POR |
Bits 13:11 – SERCOM_HSEN[2:0] SERCOMx (Direct) Enable, Bit 13=SERCOM2, Bit 12=SERCOM1, Bit 11=SERCOM0
Note: This bit is only writable when CFGLOCK[1:0] is ‘
00’.| Value | Description |
|---|---|
| 1 | Enables SERCOMx via Direct Mode (High-Speed) |
| 0 | Enables SERCOMx via PPS |
Bit 10 – QSPI_HSEN QSPI (Direct) Enable
Note: This bit is only writable when CFGLOCK[1:0] is ‘
00’.| Value | Description |
|---|---|
| 1 | Enables QSPI via Direct Mode (High-Speed) |
| 0 | Enables QSPI via PPS |
Bit 9 – CMP1_OE Analog Comparator-1 Output Enable
Note: This bit is only writable when CFGLOCK[1:0] is ‘
00’.| Value | Description |
|---|---|
| 1 | AC1 output is enabled |
| 0 | AC1 output is disabled |
Bit 8 – CMP0_OE Analog Comparator-0 Output Enable
Note: This bit is only writable when CFGLOCK[1:0] is
‘
00’.| Value | Description |
|---|---|
| 1 | AC0 output is enabled |
| 0 | AC0 output is disabled |
Bit 7 – ZBTWKSYS ZBT Subsystem External Wake-up source
Note:
- Write-only bit, with read-as zero; when ‘
1’ is written, creates one pulse on the ZBT subsystem.external_NMI0 pin. This enables external system wake-up to ZBT subsystem. This allows CPU and ZBT subsystem wake-up/sleep to be independent of each other. - Flash fuse loading is excluded for this bit.
Bit 6 – CCL_OE CCL Pads (via PPS) Output Enable
Note: This bit is only writable when CFGLOCK[1:0] =
00.| Value | Description |
|---|---|
| 1 | CCL pads (via PPS) output is enabled |
| 0 | CCL pads (via PPS) output is disabled |
Bit 5 – TRCEN Trace Enable
Note: This bit is only writable when CFGLOCK[1:0] is ‘
00’.| Value | Description |
|---|---|
| 1 | Trace features in the CPU are enabled |
| 0 | Trace features in the CPU are disabled |
Bit 2 – CAN0_PIN_EN CAN0 Pin Enable
Note: This bit is only writable when CFGLOCK[1:0] is
‘
00’.| Value | Description |
|---|---|
| 1 | CAN0 pins are enabled |
| 0 | CAN0 pins are disabled |