50.7.37 PWM Comparison n Value Update Register
This register acts as a double buffer for the CV and CVM values. This prevents an unexpected comparison n match.
Only the first 16 bits (channel counter size) of field CVUPD are significant.
CAUTION: The write of the
register PWM_CMPVUPDn must be followed by a write of the register PWM_CMPMUPDn.
| Name: | PWM_CMPVUPDn |
| Offset: | 0x0134 + n*0x10 [n=0..7] |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| CVMUPD | |||||||||
| Access | W | ||||||||
| Reset | – |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CVUPD[23:16] | |||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CVUPD[15:8] | |||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CVUPD[7:0] | |||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – | |
Bit 24 – CVMUPD Comparison x Value Mode Update
Note: This bit is not relevant if the counter of the channel 0 is left-aligned (CALG = 0
in PWM
Channel Mode Register)
| Value | Description |
|---|---|
| 0 | The comparison n between the counter of the channel 0 and the comparison n value is performed when this counter is incrementing. |
| 1 | The comparison n between the counter of the channel 0 and the comparison n value is performed when this counter is decrementing. |
Bits 23:0 – CVUPD[23:0] Comparison n Value Update
Define the comparison n value to be compared with the counter of the channel 0.