50.7.48 PWM Channel n Mode Update Register
This register can only be written if bits WPSWS2 and WPHWS2 are cleared in the PWM Write Protection Status Register.
This register acts as a double buffer for the CPOL value. This prevents an unexpected waveform when modifying the polarity value.
| Name: | PWM_CMUPDn |
| Offset: | 0x0400 + n*0x20 [n=0..3] |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CPOLINVUP | CPOLUP | ||||||||
| Access | W | W | |||||||
| Reset | – | – |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | |||||||||
| Reset |
Bit 13 – CPOLINVUP Channel Polarity Inversion Update
If this bit is written at ‘1’, the write of the bit CPOLUP is not taken into account.
| Value | Description |
|---|---|
| 0 |
No effect. |
| 1 |
The OCx output waveform (output from the comparator) is inverted. |
Bit 9 – CPOLUP Channel Polarity Update
The write of this bit is taken into account only if the bit CPOLINVUP is written at ‘0’ at the same time.
| Value | Description |
|---|---|
| 0 |
The OCx output waveform (output from the comparator) starts at a low level. |
| 1 |
The OCx output waveform (output from the comparator) starts at a high level. |