50.7.38 PWM Comparison n Mode Register
| Name: | PWM_CMPMn |
| Offset: | 0x0138 + n*0x10 [n=0..7] |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CUPRCNT[3:0] | CUPR[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CPRCNT[3:0] | CPR[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CTR[3:0] | CEN | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
Bits 23:20 – CUPRCNT[3:0] Comparison n Update Period Counter
Reports the value of the comparison n update period counter.
Note: The field CUPRCNT is read-only.
Bits 19:16 – CUPR[3:0] Comparison n Update Period
Defines the time between each update of the comparison n mode and the comparison n value. This time is equal to CUPR+1 periods of the channel 0 counter.
Bits 15:12 – CPRCNT[3:0] Comparison n Period Counter
Reports the value of the comparison n period counter.
Note: The field CPRCNT is read-only.
Bits 11:8 – CPR[3:0] Comparison n Period
CPR defines the maximum value of the comparison n period counter (CPRCNT). The comparison n value is performed periodically once every CPR+1 periods of the channel 0 counter.
Bits 7:4 – CTR[3:0] Comparison n Trigger
The comparison n is performed when the value of the comparison x period counter (CPRCNT) reaches the value defined by CTR.
Bit 0 – CEN Comparison n Enable
| Value | Description |
|---|---|
| 0 | The comparison n is disabled and can not match. |
| 1 | The comparison n is enabled and can match. |