50.7.39 PWM Comparison n Mode Update Register
This register acts as a double buffer for the CEN, CTR, CPR and CUPR values. This prevents an unexpected comparison n match.
| Name: | PWM_CMPMUPDn |
| Offset: | 0x013C + n*0x10 [n=0..7] |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CUPRUPD[3:0] | |||||||||
| Access | W | W | W | W | |||||
| Reset | – | – | – | – | |||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CPRUPD[3:0] | |||||||||
| Access | W | W | W | W | |||||
| Reset | – | – | – | – | |||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CTRUPD[3:0] | CENUPD | ||||||||
| Access | W | W | W | W | W | ||||
| Reset | – | – | – | – | – | ||||
Bits 19:16 – CUPRUPD[3:0] Comparison n Update Period Update
Defines the time between each update of the comparison n mode and the comparison n value. This time is equal to CUPR+1 periods of the channel 0 counter.
Bits 11:8 – CPRUPD[3:0] Comparison n Period Update
CPR defines the maximum value of the comparison n period counter (CPRCNT). The comparison n value is performed periodically once every CPR+1 periods of the channel 0 counter.
Bits 7:4 – CTRUPD[3:0] Comparison n Trigger Update
The comparison n is performed when the value of the comparison n period counter (CPRCNT) reaches the value defined by CTR.
Bit 0 – CENUPD Comparison n Enable Update
| Value | Description |
|---|---|
| 0 | The comparison n is disabled and can not match. |
| 1 | The comparison n is enabled and can match. |