17.3.19 ITC Math Sequence Commands Word x Register
Legend: r = Reserved Bit; R = Readable Bit; W = Writable Bit; U =
Unimplemented Bit, read as '0'; -n = Value at POR;
'1' = Bit is set; '0' = Bit is cleared; x =
Bit value is unknown
| Name: | SMATHCMDx |
| Offset: | 0x7C3040, 0x7C3044, 0x7C3048, 0x7C304C, 0x7C3050, 0x7C3054, 0x7C3058, 0x7C305C, 0x7C3060, 0x7C3064, 0x7C3068, 0x7C306C, 0x7C3070, 0x7C3074, 0x7C3078, 0x7C307C |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| END | INT | FIRST | CMP | ACCCLR | |||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| LAST | ACCA | ACCB | WMOV | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| WM[1:0] | F[1:0] | BIN[1:0] | AIN[1:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 23 – END Last Command in Sequence bit
| Value | Description |
|---|---|
1 |
This command is last in the sequence. |
0 |
There is the next command after this command. |
Bit 22 – INT Interrupt Request bit
| Value | Description |
|---|---|
| 1 | The interrupt is generated by this command. |
| 0 | The interrupt is not generated by this command. |
Bit 21 – FIRST Zero for First Accumulation Enable bit
| Value | Description |
|---|---|
| 1 | The input B is forced to zero when the first accumulation is executed. |
| 0 | Normal operation when input B is selected by the BIN[1:0] bits. |
Bit 17 – CMP Compare Accumulator A bit
| Value | Description |
|---|---|
1 |
This command compares Accumulator A with thresholds in the ITCLSxCMPLO and ITCLSxCMPHI registers as defined in the CM[2:0] bits of the ITCLSxCON register. |
0 |
The comparison is disabled. |
Bit 16 – ACCCLR Accumulator A and B Clear Request bit
| Value | Description |
|---|---|
| 1 | The accumulators A and B are cleared by this command. |
| 0 | Normal operation for the accumulators A and B. |
Bit 15 – LAST Last Accumulation Execution Enable bit
| Value | Description |
|---|---|
| 1 | The interrupt and comparison specified by the INT and CMP bits in this command are executed for the last accumulation only. |
| 0 | During normal operation, the interrupt and comparison are always executed. |
Bit 12 – ACCA Latch Result into Accumulator A bit
| Value | Description |
|---|---|
1 |
This command latches the math result into Accumulator A. |
0 |
Accumulator A is not updated. |
Bit 11 – ACCB Latch Result into Accumulator B bit
| Value | Description |
|---|---|
1 |
This command latches the math result into Accumulator B. |
0 |
Accumulator B is not updated. |
Bit 10 – WMOV Write Mode Overwrite bit
| Value | Description |
|---|---|
1 |
The Result Write mode is replaced with settings in the WM[1:0] bits of this command word. |
0 |
The Result Write mode is defined by the WM[1:0] bits in the ITCLSxCON register. |
Bits 7:6 – WM[1:0] Command Write Mode bits
| Value | Description |
|---|---|
3 |
Results are saved when a match does not occur. |
2 |
No results are saved. |
1 |
Results are saved when a match occurs. |
0 |
All result data are always saved. |
Bits 5:4 – F[1:0] Math Operation Select bits
| Value | Description |
|---|---|
3 |
BIN - AIN |
2 |
BIN + AIN |
1 |
BIN |
0 |
AIN |
Bits 3:2 – BIN[1:0] Input B Select bits
| Value | Description |
|---|---|
3 |
ADC3 conversion result |
2 |
Reserved |
1 |
Accumulator B |
0 |
ITCRESx result register |
Bits 1:0 – AIN[1:0] Input A Select bits
| Value | Description |
|---|---|
3 |
ADC3 conversion result |
2 |
Reserved |
1 |
Accumulator A |
0 |
Zero |