17.3.21 ITC Math Sequence Commands
Array Map Register
Legend: r = Reserved bit; R = Readable Bit; W = Writable Bit; U =
Unimplemented Bit, read as '0'; -n = Value at POR;
'1' = Bit is set; '0' = Bit is cleared; x =
Bit value is unknown
| Name: | SMATHMAP |
| Offset: | 0x7C3084 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | | | MATHSEQ3[3:0] | SPLIT3[1:0] | |
| Access | | | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | | | 1 | 1 | 1 | 1 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | | | MATHSEQ2[3:0] | SPLIT2[1:0] | |
| Access | | | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | | | 1 | 1 | 1 | 1 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | | | MATHSEQ1[3:0] | SPLIT1[1:0] | |
| Access | | | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | | | 1 | 1 | 1 | 1 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | MATHSEQ0[3:0] | SPLIT0[1:0] | |
| Access | | | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | | | 1 | 1 | 1 | 1 | 0 | 0 | |
Bits 29:26 – MATHSEQ3[3:0] Math Sequence Number Bits for Commands from
ITCSMATHCMD12 to ITCSMATHCMD15
These bits must
match the MSEQ[3:0] bits settings in the acquisition command ITC SDATACMDx
register.
Bits 25:24 – SPLIT3[1:0] Several Sequences
Split Bits for Commands from ITCSMATHCMD12 to ITCSMATHCMD15
Bits 21:18 – MATHSEQ2[3:0] Math Sequence
Number Bits for Commands from ITCSMATHCMD8 to ITCSMATHCMD11
These bits must match the
MSEQ[3:0] bits settings in the acquisition command ITCSDATACMDx
register.
Bits 17:16 – SPLIT2[1:0] Several Sequences
Split bits for Commands from ITCSMATHCMD8 to ITCSMATHCMD11
Bits 13:10 – MATHSEQ1[3:0] Math Sequence
Number Bits for Commands from ITCSMATHCMD4 to ITCSMATHCMD7
These bits must match the
MSEQ[3:0] bits settings in the acquisition command ITCSDATACMDx
register.
Bits 9:8 – SPLIT1[1:0] Several Sequences
Split Bits for Commands from ITCSMATHCMD4 to ITCSMATHCMD7
Bits 5:2 – MATHSEQ0[3:0] Math Sequence
Number Bits for Commands from ITCSMATHCMD0 to ITCSMATHCMD3
These bits must match the
MSEQ[3:0] bits settings in the acquisition command ITCSDATACMDx
register.
Bits 1:0 – SPLIT0[1:0] Several Sequences
Split Bits for Commands from ITCSMATHCMD0 to ITCSMATHCMD3
