17.3.8 List x Control Register

Legend: HC = Bit is Cleared by Hardware; HS = Bit is Set by Hardware; R = Readable Bit; W = Writable Bit; U = Unimplemented Bit, read as '0'; -n = Value at POR; '1' = Bit is set; '0' = Bit is cleared; x = Bit value is unknown

Name:	ITCLSxCON
Offset:	0x39C, 0x3B8, 0x3D4


Bit	31	30	29	28	27	26	25	24
	MODE[2:0]			WM[1:0]		CM[2:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	DMAEN		MULEN	SAMC[4:0]
Access	R/W		R/W	R/W	R/W	R/W	R/W	R/W
Reset	0		0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	TRGEN	SAMP	TRGCLR	SSRC[4:0]
Access	HS	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
			RECCNT[5:0]
Access			R/W	R/W	R/W	R/W	R/W	R/W
Reset			0	0	0	0	0	0

Bits 31:29 – MODE[2:0] List x Mode Selection bits

Value	Description
`7`	One trigger executes all records in back-to-back processing. The list interrupt is generated after the last list record is processed if at least one record’s result matches the comparator criteria.
`6`	One trigger executes all records in back-to-back processing. The list interrupts are generated for records every time the result matches the comparator criteria.
`5`	One trigger executes all records in back-to-back processing. The list interrupt is generated after the last record is processed.
`4`	One trigger executes all records in back-to-back processing. The list interrupts are not generated.
`3`	Reserved
`2`	One record is processed per trigger. The list interrupt is generated after the last record is processed.
`1`	One record is processed per trigger. The list interrupt is generated after each record is processed.
`0`	One record is processed per trigger. The list interrupts are not generated by the list.

Bits 28:27 – WM[1:0] Result Write Mode Selection bits

Value	Description
`3`	Results are saved when a match does not occur.
`2`	No results are saved.
`1`	Results are saved when a match occurs.
`0`	All result data are always saved.

Bits 26:24 – CM[2:0] Comparison Mode Selection bits

Value	Description
`7-5`	Reserved
`4`	Match Outside Window (Accumulator A < ITCLSnCMPLO and Accumulator A > ITCLSnCMPHI).
`3`	Match Inside Window (ITCLSnCMPLO < Accumulator A < ITCLSnCMPHI).
`2`	Match Greater Than (Accumulator A > ITCLSnCMPHI).
`1`	Match Less Than (Accumulator A < ITCLSnCMPLO).
`0`	Comparison is disabled.

Bit 23 – DMAEN DMA Triggers to Load New Command Enable bit

Value	Description
`1`	DMA triggers are enabled.
`0`	ITC does not generate DMA triggers.

Bit 21 – MULEN Multiple Inputs Connection Enable bit

Allow CVDANx pins, as defined by the ITCLSnMUL register list, to be connected together.

Value	Description
`1`	CVDANx pins defined in the ITCLSnMUL register are connected together.
`0`	All CVDANx pins are separate.

Bits 20:16 – SAMC[4:0] Balance Counter bits

Value	Description
`31`	31 T_ADs
...
`1`	1 T_ADs
`0`	0 T_ADs

Bit 15 – TRGEN List Trigger Enable bit

Value	Description
`1`	List trigger is enabled.
`0`	List trigger is disabled.

Bit 14 – SAMP Balance Switch Control bit

Value	Description
`1`	Closes the internal switch between the CVDANx pin and a CVD capacitor when the software trigger source is selected (SSRC bits = 0).
`0`	Opens a CVDANx switch and starts the conversion when the software trigger source is selected (SSRC = `0`).

Bit 13 – TRGCLR Trigger Clear bit

Value	Description
`1`	TRGEN is cleared by hardware after a trigger is received by this list.
`0`	TRGEN is only cleared by software.

Bits 12:8 – SSRC[4:0] Trigger Source Select bits

Value	Description
21	ADTRG31 (PPS)
20	QEI1
19	CCP4
18	CCP3
17	CCP2
16	PTG
15	CCP1
14	CLC4
13	CLC3
12	CLC2
11	CLC1
10	CCP5
9	PWM4 Trigger 2
8	PWM4 Trigger 1
7	Internal timer periodic trigger as set up by TMRPR bits in the ITCCON2 register.
6	PWM3 Trigger 2
5	PWM3 Trigger 1
4	PWM2 Trigger 2
3	PWM2 Trigger 1
2	PWM1 Trigger 2
1	PWM1 Trigger 1
0	Software trigger is controlled by a SAMP bit. A single trigger is generated when SAMP transitions from 1 to 0.

Bits 5:0 – RECCNT[5:0] Number of Records in List bits

Value	Description
63-33	Reserved
32	32
...
1	1
0	0