17.3.18 ITC Acquisition Sequence Commands Word x Register

Legend: r = Reserved Bit; R = Readable Bit; W = Writable Bit; U = Unimplemented Bit, read as '0'; -n = Value at POR; '1' = Bit is set; '0' = Bit is cleared; x = Bit value is unknown

Name:	SDATACMDx
Offset:	0x7C3000, 0x7C3004, 0x7C3008, 0x7C300C, 0x7C3010, 0x7C3014, 0x7C3018, 0x7C301C, 0x7C3020, 0x7C3024, 0x7C3028, 0x7C302C, 0x7C3030, 0x7C3034, 0x7C3038, 0x7C303C


Bit	31	30	29	28	27	26	25	24
	END	LOOP[3:0]				DMASTP	DMATXC	DMATXB
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	DMATXA	DMALAST	DMALACC	MSTART	MSEQ[3:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	CHRG	DISCHRG	CONV	BAL
Access	R/W	R/W	R/W	R/W
Reset	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	PCC[1:0]		PCB[1:0]		PCA[1:0]		PC0[1:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 31 – END Last Command in Sequence bit

Value	Description
`1`	This command is last in the sequence.
`0`	There is the next command after this command.

Bits 30:27 – LOOP[3:0] Wait bits

Value	Description
`12-15`	Reserved
11	The command waits for the new command that has been sent by DMA to the SDATACMDx register.
10	The command waits for Timer D with delay defined by the TMRD[7:0] bits in the ITCLSxTMR register.
9	The command waits for Timer C with delay defined by the TMRC[7:0] bits in the ITCLSxTMR register.
5-8	Reserved
4	The command waits for the ADC’s end of conversion.
3	The command waits for delay defined in the SAMC[4:0] bits in the ITCLSxCON register.
`2`	The command waits for Timer B with delay defined by the TMRB[7:0] bits in the ITCLSxTMR register.
`1`	The command waits for Timer A with delay defined by the TMRA[7:0] bits in the ITCLSxTMR register.
`0`	No delay, the next instruction must be executed right away.

Bit 26 – DMASTP DMA Transfer of New Command Trigger bit

The DMA must update/write the ITCSDATACMDx register to clear the DMA trigger.

Value	Description
`1`	This command requests the DMA to transfer new commands in the ITCSDATACMDx registers.
`0`	DMA is not requested.

Bit 25 – DMATXC DMA Transfer to Update ITCTXC Register Trigger bit

The DMA must update/write the ITCTXC register to clear the DMA trigger.

Value	Description
`1`	This command requests the DMA to transfer a new value to the ITCTXC register.
`0`	DMA is not requested.

Bit 24 – DMATXB DMA Transfer to Update ITCTXB Register Trigger bit

The DMA must update/write the ITCTXB register to clear the DMA trigger.

Value	Description
`1`	This command requests the DMA to transfer a new value to the ITCTXB register.
`0`	DMA is not requested.

Bit 23 – DMATXA DMA Transfer to Update ITCTXA Register Trigger bit

The DMA must update/write the ITCTXA register to clear the DMA trigger.

Value	Description
`1`	This command requests the DMA to transfer a new value to the ITCTXA register.
`0`	DMA is not requested.

Bit 22 – DMALAST DMA Transfer Only If All Records Are Processed Enable bit

Value	Description
1	DMA triggers specified by DMASTEP, DMATXA, DMATXB and DMATXC bits are sent only when the last record in the last scan is processed.
0	DMA triggers specified by DMASTEP, DMATXA, DMATXB and DMATXC bits are always executed.

Bit 21 – DMALACC DMA Transfer Each Time When a Record is Accumulated Last Time Enable bit

Value	Description
1	DMA triggers specified by DMASTEP, DMATXA, DMATXB and DMATXC bits are sent only when the record is accumulated last time.
0	DMA triggers specified by DMASTEP, DMATXA, DMATXB and DMATXC bits are always executed.

Bit 20 – MSTART Post-Processing Math Sequence Start bit

Value	Description
`1`	This command executes the math sequence.
`0`	The math sequence is not executed.

Bits 19:16 – MSEQ[3:0] MSEQ Math Post-Processing Sequence Number bits

Value	Description
15	Math sequence 15
...
1	Math sequence 1
0	Math sequence 0

Bit 15 – CHRG CVD Capacitors Array Charge bit

Value	Description
`1`	The command will connect the CVD capacitors array to V_DD (power).
`0`	The charge switch is open.

Bit 14 – DISCHRG CVD Capacitors Array Discharge bit

Value	Description
`1`	The command will connect the CVD capacitors array to V_SS (ground).
`0`	The discharge switch is open.

Bit 13 – CONV ADC3 Conversion Request bit

Value	Description
`1`	The command will start an ITC conversion of CVD capacitors array level.
`0`	The conversion is not requested.

Bit 12 – BAL Balance Charge bit

Value	Description
`1`	The command will connect the CVD capacitors array to the sensor CVDANx pin.
`0`	The balance switch is open.

Bits 7:6 – PCC[1:0] ITCTXC Register Level bits

Value	Description
`3`	CVDTXx pins defined in the ITCTXC register are tri-stated.
`2`	CVDTXx pins defined in the ITCTXC register are set to a high level.
`1`	CVDTXx pins defined in the ITCTXC register are set to a low level.
`0`	ITCTXC register is not used, the pins defined in ITCTXC are controlled by TRIS and LAT registers.

Bits 5:4 – PCB[1:0] ITCTXB Register Level bits

Value	Description
`3`	CVDTXx pins defined in the ITCTXB register are tri-stated.
`2`	CVDTXx pins defined in the ITCTXB register are set to a high level.
`1`	CVDTXx pins defined in the ITCTXB register are set to a low level.
`0`	ITCTXB register is not used, the pins defined in ITCTXB are controlled by TRIS and LAT registers.

Bits 3:2 – PCA[1:0] ITCTXA Register Level bits

Value	Description
`3`	CVDTXx pins defined in the ITCTXA register are tri-stated.
`2`	CVDTXx pins defined in the ITCTXA register are set to a high level.
`1`	CVDTXx pins defined in the ITCTXA register are set to a low level.
`0`	ITCTXA register is not used, the pins defined in ITCTXBA are controlled by TRIS and LAT registers.

Bits 1:0 – PC0[1:0] CVDANx Pin Level Bits

Value	Description
`3`	CVDANx pins are tri-stated.
`2`	CVDANx pins are set to a high level.
`1`	CVDANx pins are set to a low level.
`0`	CVDANx is not used, the pin is controlled by TRIS and LAT registers.