17.3.20 ITC Math Sequence Commands Array Map Register

Legend: r = Reserved Bit; R = Readable Bit; W = Writable Bit; U = Unimplemented Bit, read as '0'; -n = Value at POR; '1' = Bit is set; '0' = Bit is cleared; x = Bit value is unknown

Name: SDATAMAP
Offset: 0x7C3080

Bit 3130292827262524 
   DATASEQ3[2:0] SPLIT3[1:0] 
Access R/WR/WR/WR/WR/W 
Reset 11100 
Bit 2322212019181716 
   DATASEQ2[2:0] SPLIT2[1:0] 
Access R/WR/WR/WR/WR/W 
Reset 11100 
Bit 15141312111098 
   DATASEQ1[2:0] SPLIT1[1:0] 
Access R/WR/WR/WR/WR/W 
Reset 00000 
Bit 76543210 
   DATASEQ0[2:0] SPLIT0[1:0] 
Access R/WR/WR/WR/WR/W 
Reset 11100 

Bits 29:27 – DATASEQ3[2:0] Acquisition Sequence Number Bits for Commands from ITCSDATACMD12 to ITCSDATACMD15

These bits must match the DATASEQ[2:0] bits settings in the ITCSLxSEQ register.

Bits 25:24 – SPLIT3[1:0] Several Sequences Split Bits for Commands from ITCSDATACMD12 to ITCSDATACMD15

Bits 21:19 – DATASEQ2[2:0] Acquisition Sequence Number Bits for Commands from ITCSDATACMD8 to ITCSDATACMD11

These bits must match the DATASEQ[2:0] bits settings in the ITCSLxSEQ register.

Bits 17:16 – SPLIT2[1:0] Several Sequences Split Bits for Commands from ITCSDATACMD8 to ITCSDATACMD11

Bits 13:11 – DATASEQ1[2:0] Acquisition Sequence Number Bits for Commands from ITCSDATACMD4 to ITCSDATACMD7

These bits must match the DATASEQ[2:0] bits settings in the ITCSLxSEQ register.

Bits 9:8 – SPLIT1[1:0] Several Sequences Split Bits for Commands from ITCSDATACMD4 to ITCSDATACMD7

Bits 5:3 – DATASEQ0[2:0] Acquisition Sequence Number Bits for Commands from ITCSDATACMD0 to ITCSDATACMD3

These bits must match the DATASEQ[2:0] bits settings in the ITCSLxSEQ register.

Bits 1:0 – SPLIT0[1:0] Several Sequences Split Bits for Commands from ITCSDATACMD0 to ITCSDATACMD3