24.4.4.5.5 High Data Rate-Double Data Rate (HDR-DDR) Transfers

The HDR-DDR write and read transfers are initiated on the bus based on the I3CxCMDQUE and settings shown in Table 24-13.

The HDR Transfers are supported only with the ‘Transfer Argument command’ and not with the ‘Short Data Argument command’ since, at most, two words can be transferred in the Short Data Argument command format, and it really does not justify the overhead in terms of ENTHDR* CCC, HDR Command, entry and exit patterns.

The controller generates the ‘ENTHDR0’ CCC to enter into the HDR-DDR mode and forms the Command code through the CMD field of the Transfer command and target address. The preamble and parity bits are generated by the controller as per the protocol and sent along with the write data word. The word from the Tx-FIFO is appended with the parity bits and preamble bits to form the Write Data word and transmits the data. The HDR-RESTART and HDR-EXIT patterns are generated in place of the RESTART and STOP conditions.

To avoid the initial latencies of the transfer, the controller uses TXSTART/RXSTART in the I3CxBUFTHLD register before initiating the transfer. TXSTART ensures the threshold level of data is present in the Transmit buffer for a write transfer, and RXSTART ensures the level of space is available in the Receive buffer for a read transfer before initiating the transfer. This threshold is only applicable for transfers initiated with the START condition and not applicable for transfers initiated with the RESTART condition. If the threshold amount of write data in the Tx-FIFO or empty space in the Rx-FIFO is not available, the controller waits until the threshold amount of data is available to initiate the transfer. If the threshold amount of data is not available for the HDR-DDR transfer initiated, which must be initiated with RESTART, then the controller generates an EXIT pattern followed by STOP for the current transfer and waits for the threshold amount of data to initiate the next transfer with a START condition.

The controller halts in the case of the following conditions:

• Receiving NACK for the address header of the private transfers.
• Receiving NACK for the target address (HDR-CMD) of the HDR-DDR private transfers.
• If the controller experiences Transfer Underflow or Receive Overflow during the HDR-DDR transfers.
• After executing a software-initiated terminate.
• The controller decodes the parity bits, CRC byte, frame mismatch, and validates them for the read transfer and reports in the ‘ERR_STS’ field of the response status (I3CxRESPQUE) if there is any error.

The controller updates the ‘ERR_STS’ field with appropriate error information in the response status, halts the controller, and gives back control to the application to resume the operation of the controller by writing ‘1’ to the Resume bit of the I3CxCTRL register.