24.4.5.2.1 Handling Private Receive (Controller Write) Transfers

In SDR mode of operation, the Target accepts the write address (ACK response) when all of the following conditions are met:

  • The Receive Buffer has space (in terms of empty locations) equal to or more than the programmed value of the I3C1BUFTHLD [RXSTART].
  • The Response Queue is not full, and it has some space to hold the response for the current transfer.
Otherwise, the Target responds with a NACK for the private write address.
Note: The frequency of the responses for the write transfer is controlled by the threshold I3CxECRTCON [RSPDATTHLD]. It indicates after how many data bytes a new transfer is generated. For the last response of the transfer, the indicated data length is less than or equal to the threshold I3CxECRTCON [RSPDATTHLD]. The data structure of the response is in Response Data Structure.

Once the write address is acknowledged with ACK (accepted), the Target expects the RX FIFO space to be available until the end of the transfer to avoid an overflow condition. In the non-DMA mode of operation, use either the I3C1INTSTA[RXTHLDSTA] interrupt to free up the RX FIFO space while the RX data is being received, or configure the RX FIFO to accommodate the entire write transfer data (when the maximum write transfer size is defined and small). In the DMA mode of operation, the DMA request of the handshake interface is initiated when the RX FIFO level reaches the programmed I3C1BUFTHLD [RXBUF] level.

When an overflow condition is encountered (when the system latency is too high to consume the receiving data), the Target sets the I3CxCLTCCCSTAT [OVFLWERR] bit of the register and drops the further incoming data until the termination (either STOP or RESTART) is detected.

When a parity error is encountered during the Controller write transfer, the Controller sets the I3CxCLTCCCSTAT [PROTOERR] bit of the register and drops the further incoming data until the termination is detected.

Once the Target sets the overflow error or protocol error bit, it rejects (NACK) any further private or Vendor Specific CCC transfer requests from the Controller until the Controller reads the Target status through a GETSTATUS CCC, and the Target application resumes the Target operation by setting the bit I3CxCNTRL [RESUME].

If the receive FIFO does not have a threshold amount of space to accommodate the write transfer, the Controller NACKs the request and the I3CxCLTCCCSTAT [BUFFNTAVAIL] bit is set. Once the buffer not available bit is set, it rejects (NACKs) any further private write transfer requests from the Controller until space is available in the receive FIFO.

Note: In I2C mode of operation, if an overflow error is encountered in a write transfer, the Target terminates the ongoing transfer by sending a NACK. It rejects (NACKs) any further private transfer requests from the Controller until the Target application resumes the Target operation by setting the bit I3CxCNTRL [RESUME].
Figure 24-37. Private Receive Transfer