24.4.5.2.2 Handling Private Transmit (Controller Read) Transfers
The data transmission for a private Controller read is initiated by issuing a TX transfer command. The TX transfer command can be issued by writing the TX command data structure into the I3CxCMDQUE register (refer to Transmit Command Data Structure). The Target responds to a private read address with ACK when all of the following conditions are met:
- TX Command is valid in the Command Queue.
- TX FIFO has data equal to either the data length size of the command or the I3CxBUFTHLD[TXSTART] size is met.
- Response Queue Non-Full.
Otherwise, the Target responds with a NACK for the private read address.
To determine under which condition the NACK occurred, the Controller provides further information as follows:
- An additional interrupt, I3CxINTSTA [READREQSTA], is asserted when there is no valid command in the Command Queue.
- The I3CxCLTCCCSTAT [DATNTRDY] bit is set when the Extended TX FIFO corresponding to the programmed and matched I3CxEXTCMDy is empty.
- The I3CxCLTCCCSTAT [DATNTRDY] bit is also set if the Response Queue is full.
During HDR transfers (ENTHDR CCC detected), the Target responds with either a "Target NACK" preamble to indicate the Target's inability to transmit the data for the private read command when one of the conditions is not met.
Once the read address is acknowledged with ACK (accepted), the Target expects the application to provide enough data in the TX FIFO to avoid underrun conditions. It is recommended to program enough data in the corresponding I3CxEXTTXDATy before programming the command in its equivalent I3CxEXTCMDy register.
In the non-DMA operation, use the I3CxINTCON[TXTHLDINTEN] interrupt to fill the TX FIFO while the TX data is being transmitted on the I3C bus. In the DMA mode of operation, the DMA request of the handshake interface is initiated when the TX FIFO empty location level reaches the programmed I3CxBUFTHLD[TXTHLD] level.
When an underrun condition is encountered (when the system latency is too high to provide the transmit data), the Target sets the I3CxCLTCCCSTAT[UDFLWERR] bit and terminates the transfer on the I3C bus.
Once the Target sets the I3CxCLTCCCSTAT [UDFLWERR] bit, it rejects (NACK) any further private transfer requests from the Controller until the Controller reads the device status through a GETSTATUS CCC, and the Target application resumes the Target operation by setting the I3CxCNTRL [RESUME] bit of the register.
If the transmit FIFO does not have the threshold amount of data to respond to the Controller's read request, the Target NACKs the request, and the I3CxCLTCCCSTAT [DATNTRDY] bit is set. Once the Target sets the I3CxCLTCCCSTAT [DATNTRDY] bit, it rejects (NACK) any further private read transfer requests from the Controller until data is available in the transmit FIFO.