18.4.2.1 ADC Input Selection and Coherent Demodulation

The RDC will automatically trigger the ADC for coherent sampling. The RDCINSEL register allows the selection of the ADC instance and channel used to sample the sine and cosine outputs from the resolver.

The IMUX0 (RDCINSEL[2:0]) and IMUX1 (RDCINSEL[18:16]) bit fields can select the ADC module instances that receive the resolver output to be demodulated. For resolver outputs, the user should configure the ADC to oversample the input signals at a multiple “N” of the excitation frequency; this will be inherently true if using the excitation and trigger frequencies produced by this module due to the availability of the signal dividers using EXCFDIV bits.

If the ADC of the dsPIC33AK256MPS306 family of devices is used, then the resolver output can be connected as input to multiple channels of the ADC. In this case, the ICHAN0 (RDCINSEL[7:3]) and ICHAN1 (RDCINSEL[23:19]) bit fields can select the ADC channels to use for the ADC module instance selected by IMUX0 and IMUX1, respectively. If the IMUX0 and IMUX1 values do not correspond to a valid ADC module instance available in the device, then the IMUXCFGERR (RDCSTAT[1]) bit will be set to '1'. CIC filter channel x (x=0,1) will be fed with digital samples from the corresponding ADC channel selected by ICHANx of the ADC module instance selected by IMUXx. When selecting channels that are sampled sequentially on one input source or which are sampled on different sources with some phase difference, care should be taken to sample the inputs as close to synchronously as possible to minimize output error.