18.4.2.2 Excitation Signal Feedback Delay

To correctly demodulate the resolver output signals, the excitation signal polarity input should be in phase with the resolver outputs produced by that excitation signal. The EXCFBDLY (RDCEXCDLY[15:8]) bits can introduce a 1-256 UPB cycle clock delay to the excitation signal feedback value to compensate for any delay introduced by the resolver, external circuitry, or ADC sampling time. It may be possible to configure the EXCFBDLY to produce a delay longer than the half-period of the excitation signal, which would prevent correct module operation. It is the user’s responsibility to appropriately configure the delay to avoid this.