18.4.2.1.1 ADC Trigger Signals

To generate the trigger signal to the ADC, the RDC module will divide the input clock by four and delay it by ADCTRGDLY clocks.

$F_{TRIG}=\frac{F_{RDCCLK}}{4}$

Where F_TRIG is the frequency at which the ADC is triggered by the RDC.

Deriving the excitation signal from the ADC trigger signal creates the possibility that the ADC may sample its inputs during the excitation signal transitions. To prevent this, the ADCTRGDLY (RDCEXCDLY[1:0]) delay bits will add a configurable phase delay between the RDC excitation output and ADC trigger signals. This delay value is selected in clock periods of the RDC input clock and is configurable to allow greater synchronization of outputs with a controlling firmware process.