29.3.6 Synchronization

The Control A (CTRLA) register is synchronized when written due to the asynchronicity between the WDT clock domain and the peripheral clock domain. The Synchronization Busy (SYNCBUSY) flag in the STATUS (STATUS) register indicates if there is an ongoing synchronization.

Writing to the CTRLA register while SYNCBUSY = 1 is not allowed.

Synchronizing the WDR instruction requires two to three WDT clock cycles.

The CTRLB register is in the peripheral clock domain and does not need synchronization when read or written.

The CNT register is synchronized to the peripheral clock domain and can be read whenever the CNTBUSY bit is not set. This 14-bit register is not buffered by a TEMP register, so reads of the two register bytes may be inconsistent. The intended use of this register is reading it at periodic intervals, e.g., every millisecond or on every iteration of the main()-loop, and verifying that the CNTL register has approximately the expected value. Alternatively, verify the entire register during the system startup test by polling CNTBUSY until it transitions from 1 to 0 and then immediately reading CNTH and CNTL, all in an atomic operation.