15.4.14 CAN Transmit/Receive Error Count Register(1)

Note:
  1. The individual bytes in this multibyte register can be accessed with the following register names:
    • CxTRECT: Accesses the top byte TREC[31:24].
    • CxTRECU: Accesses the upper byte TREC[23:16].
    • CxTREC: Accesses the byte TREC[31:0].
Name: CxTREC
Offset: 0x2634, 0x2924

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
   TXBOTXBPRXBPTXWARNRXWARNEWARN 
Access RRRRRR 
Reset 100000 
Bit 15141312111098 
 TERRCNT[7:0] 
Access RRRRRRRR 
Reset 00000000 
Bit 76543210 
 RERRCNT[7:0] 
Access RRRRRRRR 
Reset 00000000 

Bit 21 – TXBO Transmitter in Error Bus Off State bit (TERRCNT[7:0] > 255)

In Configuration mode, TXBO is set since the module is not on the bus.

Bit 20 – TXBP Transmitter in Error Bus Passive State bit (TERRCNT[7:0] > 127)

Bit 19 – RXBP Receiver in Error Bus Passive State bit (RERRCNT[7:0] > 127)

Bit 18 – TXWARN Transmitter in Error Warning State bit (128 > TERRCNT[7:0] > 127)

Bit 17 – RXWARN Receiver in Error Warning State bit (128 > RERRCNT[7:0] > 127)

Bit 16 – EWARN Transmitter or Receiver is in Error Warning State bit

Bits 15:8 – TERRCNT[7:0] Transmit Error Counter bits

Bits 7:0 – RERRCNT[7:0] Receive Error Counter bits