15.4.33 CAN 2 FIFO x Control Register(1), (2)
Note:
- The individual bytes in this
multibyte register can be accessed with the following register names:
- C2FIFOCONyT: Accesses the top byte FIFOCONy[31:24].
- C2FIFOCONyU: Accesses the upper byte FIFOCONy[23:16].
- C2FIFOCONy: Accesses the byte FIFOCONy[31:0].
- [x] denotes FIFO number, from 1 to 7.
- These bits can only be
modified in Configuration mode (OPMOD[2:0] =
100).
| Name: | C2FIFOCONx |
| Offset: | 0x294C, 0x2958, 0x2964, 0x2970, 0x297C, 0x2988, 0x2994 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| PLSIZE[2:0] | FSIZE[4:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| TXAT[1:0] | TXPRI[4:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 1 | 1 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| FRESET | TXREQ | UINC | |||||||
| Access | S/HC | R/W/HC | S/HC | ||||||
| Reset | 1 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TXEN | RTREN | RXTSEN | TXATIE | RXOVIE | TFERFFIE | TFHRFHIE | TFNRFNIE | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 31:29 – PLSIZE[2:0] Payload Size bits(3)
| Value | Description |
|---|---|
| 111 | 64 data bytes |
| 110 | 48 data bytes |
| 101 | 32 data bytes |
| 100 | 24 data bytes |
| 011 | 20 data bytes |
| 010 | 16 data bytes |
| 001 | 12 data bytes |
| 000 | 8 data bytes |
Bits 28:24 – FSIZE[4:0] FIFO Size bits(3)
| Value | Description |
|---|---|
| 11111 | FIFO is 32 messages deep. |
| ... | |
| 00001 | FIFO is 2 messages deep. |
| 00000 | FIFO is 1 message deep. |
Bits 22:21 – TXAT[1:0] Retransmission Attempts bits
| Value | Description |
|---|---|
| 11 | Unlimited number of retransmission attempts |
| 10 | Unlimited number of retransmission attempts |
| 01 | Three retransmission attempts |
| 00 | Disables retransmission attempts |
Bits 20:16 – TXPRI[4:0] Message Transmit Priority bits
| Value | Description |
|---|---|
| 11111 | Highest message priority |
| 00000 | Lowest message priority |
Bit 10 – FRESET FIFO Reset bit
| Value | Description |
|---|---|
| 1 | FIFO will be reset when the bit is set and cleared by hardware whenever FIFO is reset. The user needs to poll whether this bit is clear before taking any action. |
| 0 | No effect |
Bit 9 – TXREQ Message Send Request bit
| Value | Name | Description |
|---|---|---|
| 1 | TXEN = 1 (FIFO configured as a transmit
FIFO) |
Requests sending a message: the bit will automatically clear when all the messages queued in the FIFO are successfully sent. |
| 0 | TXEN = 1 (FIFO configured as a transmit
FIFO) |
Clearing the bit to ‘0’ while set (‘1’)
will request a message abort. |
| x | TXEN = 0 (FIFO configured as a receive
FIFO) |
This bit has no effect. |
Bit 8 – UINC Increment Head/Tail bit
| Value | Name | Description |
|---|---|---|
| 1 | TXEN = 1 (FIFO configured as a transmit
FIFO) |
When this bit is set, the FIFO head will increment by a single message. |
| 1 | TXEN = 0 (FIFO configured as a receive
FIFO) |
When this bit is set, the FIFO tail will increment by a single message. |
Bit 7 – TXEN TX/RX Buffer Selection bit
| Value | Description |
|---|---|
| 1 | Transmits message object. |
| 0 | Receives message object. |
Bit 6 – RTREN Auto-Remove Transmit (RTR) Enable bit
| Value | Description |
|---|---|
| 1 | When a Remote Transmit is received, TXREQ will be set. |
| 0 | When a Remote Transmit is received, TXREQ will be unaffected. |
Bit 5 – RXTSEN Received Message Timestamp Enable bit(3)
| Value | Description |
|---|---|
| 1 | Captures the timestamp in a received message object in RAM. |
| 0 | Does not capture the timestamp. |
Bit 4 – TXATIE Transmit Attempts Exhausted Interrupt Enable bit
| Value | Description |
|---|---|
| 1 | Enables interrupt. |
| 0 | Disables interrupt. |
Bit 3 – RXOVIE Overflow Interrupt Enable bit
| Value | Description |
|---|---|
| 1 | Interrupt is enabled for overflow event. |
| 0 | Interrupt is disabled for overflow event. |
Bit 2 – TFERFFIE Transmit/Receive FIFO Empty/Full Interrupt Enable bit
| Value | Name | Description |
|---|---|---|
| 1 | TXEN = 1 (FIFO configured as a transmit
FIFO) |
Interrupt is enabled for FIFO empty. |
| 0 | TXEN = 1 (FIFO configured as a transmit
FIFO) |
Interrupt is disabled for FIFO empty. |
| 1 | TXEN = 0 (FIFO configured as a receive
FIFO) |
Interrupt is enabled for FIFO full. |
| 0 | TXEN = 0 (FIFO configured as a receive
FIFO) |
Interrupt is disabled for FIFO full. |
Bit 1 – TFHRFHIE Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
| Value | Name | Description |
|---|---|---|
| 1 | TXEN = 1 (FIFO configured as a transmit
FIFO) |
Interrupt is enabled for FIFO half empty. |
| 0 | TXEN = 1 (FIFO configured as a transmit
FIFO) |
Interrupt is disabled for FIFO half empty. |
| 1 | TXEN = 0 (FIFO configured as a receive
FIFO) |
Interrupt is enabled for FIFO half-full |
| 0 | TXEN = 0 (FIFO configured as a receive
FIFO) |
Interrupt is disabled for FIFO half-full. |
Bit 0 – TFNRFNIE Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
| Value | Name | Description |
|---|---|---|
| 1 | TXEN = 1 (FIFO configured as a transmit
FIFO) |
Interrupt is enabled for FIFO not full. |
| 0 | TXEN = 1 (FIFO configured as a transmit
FIFO) |
Interrupt is disabled for FIFO not full. |
| 1 | TXEN = 0 (FIFO configured as a receive
FIFO) |
Interrupt is enabled for FIFO not empty. |
| 0 | TXEN = 0 (FIFO configured as a receive
FIFO) |
Interrupt is disabled for FIFO not empty. |