1.4.1.1 AXI Master Write Transactions

Write transactions are handled in big-endian order as required by the PCI Express Base Specification. The master path does not reorder transactions, but arbitrates between transactions at the AXI4 master interface. If a transaction is currently waiting for a response phase, the transaction is allowed to complete before the read transaction is forwarded to the AXI4 master interface. The maximum number of outstanding write transactions supported in non-DMA mode is eight. PCIe transactions sizes may vary up to the configurable maximum payload size (256 bytes):

• AXI4 transactions are limited to 256 bytes, and the received TLP is divided into several AXI4 transactions.
• AXI4 master receives a write transaction, processing it in 256-byte segments.
• TLP is de-constructed from the PCIe system and sent to the AXI4 interface in little-endian format.