1.4.1.2 AXI Master Read Transactions

Read transactions are handled similar to write transactions, except that before transferring the transaction to the AXI4 master read channel, the PCIESS checks the transmit buffer for available space. If the transmit replay buffer does not have sufficient place to store the PCIe completions, the PCIESS does not transfer the read transaction. Hence, the number of outstanding AXI4 master read transactions is limited by the size of the transmit buffer. The maximum number of outstanding read transactions supported in non-DMA mode is four.

The AXI4 master read channel can receive transactions in any order, and data can be completely interleaved. However, the PCIESS generates completions in the order they are initiated on the link.