1.1.5 Low-Power States

The PCIESS supports PCIe low-power operation states known as L0s and L1 states. These states are available in both, root port, and endpoint configurations.

L0s (Autonomous electrical idle): This state reduces power during short intervals of idle. Devices must transition to L0s independently on each direction of the link.

L1 (Directed electrical idle): This state reduces power when the downstream port directs the upstream ports. This state saves power in two ways:

  • Shutting down the transceiver circuitry and associated PLL.
  • Significantly decreasing the number of internal core transitions.
Important: PCIe Link Training and Status State Machine (LTSSM) hardware blocks of PolarFire transceiver do not support the L2/P2 power management link state. The L2/P2 power management link state does not achieve further operational power-savings for the PolarFire device.

To achieve further operational power savings, on top of the already power-optimized PolarFire device architecture, the FPGA designer must employ power management techniques directly to the FPGA fabric design.

  • Software-driven L2/P2 entry commands issued by the PolarFire PCIESS Root Port to the downstream endpoints are not supported to the down-stream end-points. As a Root Port, this causes the link to be completely disrupted and only recoverable by re-initializing the link with side-band PERSTn (fundamental reset) or a power cycle.
  • PolarFire PCIESS endpoint must not be commanded by the host to enter L2/P2 link state. As an endpoint, the link might be disruptive and only recoverable by re-initializing the link with side-band PERSTn (fundamental reset) or a power cycle.
Important: The following are the debug recommendations when LTSSM does not reach L0.
  • Power OFF the host PC while inserting the PCIe Edge connector. If it is not powered OFF, the PCIe device detection and the selection of Gen1 or Gen2 mode may fail. The device detection and selection depend on the host PC PCIe configuration. When the host PC is powered ON, check if the PCIe is detected in the device manager of the host PC. For more information about Board to the host PC PCIe slot connection, see PolarFire FPGA PCIe EndPoint DDR3L DDR4 Memory Controller Data Plane.
  • Using SmartDebug, you can check LTSSM state status. For more information, see SmartDebug User Guide.
  • A third-party logic analyzer for PCI Express records the traffic on the physical link and decodes traffic. A third party logic analyzer can show the two way traffic at different levels for different requirements. For high-level diagnostics, the analyzer shows the LTSSM flows for devices on both side of the link side-by-side. This display can help you see the link training handshake behavior and identify where the traffic is stuck. You can also verify the contents of packets displayed on traffic analyzer.