50.7.18 12-bit ADC Characteristics

Table 50-40. ADC Power Supply Characteristics
Symbol	Parameter	Conditions	Min	Max	Unit
V_DD3V3	Supply voltage range	Internal voltage reference OFF⁽¹⁾ Internal voltage reference ON⁽²⁾	2.5 2.8	VDD3V3	V

Note:

VREFP must be supplied with an external voltage.
A capacitor must be connected between VREFP and GND. See the following table.

Table 50-41. ADC Voltage Reference Characteristics
Symbol	Parameter	Conditions	Min	Max	Unit
V_VREFP	Positive input voltage range	Internal voltage reference OFF only	2.5	V_DD3V3	V
V_ACC	Voltage accuracy^{(1, 2)}	–	-2.5	+2.5	%
t_ON	Start-up time⁽²⁾	–	–	100	μS
V_NOISE	Output voltage noise⁽²⁾	Integrated rms value, bandwidth 1 Hz to 500 kHz	60	100	μVrms
R_VREFP	VREFP input resistance to ground⁽²⁾	ADC ON	7.2	12	kΩ
R_VREFP	VREFP input resistance to ground⁽²⁾	ADC OFF	1	–	MΩ
R_LOADVREFP	Resistive load drive capability⁽²⁾	External load on VREFP	50	–	kΩ

Note:

A ceramic X5R or X7R capacitor of 220nF maximum on VREFP is mandatory.
Simulation data.

Table 50-42. ADC Timing Characteristics
Symbol	Parameter	Conditions	Min	Max	Unit
f_CKADC	ADC clock frequency	–	0.2	20	MHz
t_CONV	ADC conversion time⁽¹⁾	–	20	–	t_CKADC
f_S	Sampling rate⁽²⁾	–	–	1	MS/s
t_START	Start-up time⁽⁵⁾	OFF to ON⁽⁴⁾	–	4	μs
t_TRACK	Track and hold time⁽³⁾	–	300	–	ns

Note:

t_CONV= t_CH + t_TRACK + 14 x t_CKADC with t_CKADC= 1 / f_CKADC. t_CH = 0 when the ADC operates in the same input mode (single-ended or differential) for the current conversion than for the previous one. t_CH = 2 when the ADC input mode is changed to perform the current conversion.
f_S = 1 / t_CONV.
Refer to Track and Hold Time versus Source Impedance – Sampling Rate.
ADC_MR.SLEEP = 0 and ADC_MR.FWUP = 1.
Simulation data.

Table 50-43. ADC Supply Monitor
Symbol	Parameter	Conditions	Min	Max	Unit
V_IT-	Negative-going threshold voltage (VDD3V3) detection⁽¹⁾	Voltage threshold in low range Voltage threshold in high range	2.30 2.60	2.60 2.90	V
V_hys	Hysteresis	–	5	35	mV
t_DET	Detection time	–	–	20	μs
t_ON	Start-up time⁽²⁾	From OFF to ON	–	100	μs

Note:

Voltage threshold range selection from ADC_ACR.SMVT.  Low or high range detection threshold is in correlation with the VREFP voltage supply and ADC voltage supply range. See Table 50-40.
Simulation data.

Table 50-44. ADC Analog Input Characteristics
Symbol	Parameter	Conditions	Min	Max	Unit
V_FS	Analog input full scale range⁽¹⁾	ADC_COR.DIFFx = 0	0	V_VREFP	V
V_FS	Analog input full scale range⁽¹⁾	ADC_COR.DIFFx = 1	-V_VREFP	V_VREFP	V
V_INCM	Common mode input range in Differential Input mode⁽²⁾	ADC_COR.DIFFx = 1	0.4 x V_DD3V3	0.6 x V_DD3V3	V
C_S	ADC sampling capacitance⁽⁵⁾	–	–	3	pF
C_{P_ADx}	ADx input parasitic capacitance^{(4, 5)}	ADx pin configured as analog input	–	7	pF
R_ON	Internal series resistor^{(4, 5)}	VDD3V3 ≥ 1.7V	–	8	kΩ
R_ON	Internal series resistor^{(4, 5)}	VDD3V3 ≥ 2.4V	–	2	kΩ
Z_IN	Common mode input impedance^{(3, 5)}	On ADx pin	1 / (f_S.C_S)	–	Ω

Note:

V_FS = V_ADx in Single-ended mode, and V_FS= (V_ADx- V_ADx+1) in Differential mode.
V_INCM= (V_ADx + V_ADx+1) / 2.
Assuming conversion on one single channel.
With respect to the equivalent model of Figure 50-23.
Simulation data.

Figure 50-22. Acquisition Path Block Diagram

For tracking time calculation, during the sampling phase of the converter, this acquisition path can be reduced to the equivalent model of Figure 50-23 where:

R_ON = R_MUX + R_S
C_{P_ADX} = C_PX + C_{P_MUX}

Figure 50-23. Equivalent Model of the Acquisition Path

Symbol	Parameter	Conditions	Min	Max	Unit
RES_ADC	Native ADC resolution	–	12		Bits
INL	Integral non-linearity	f_CKADC = 1 MHz ADC_EMR.OSR = (000)₂	-4	+4	LSB
DNL	Differential non-linearity		-2	+2	LSB
OE	Offset error		-5	+5	LSB
GE	Gain error		-20	+20	LSB

Symbol	Parameter	Conditions	Min	Max	Unit
Single-ended Input mode (ADC_CCR.DIFFx = 0)
SNR	Signal to noise ratio	–	60	–	dB
THD	Total harmonic distortion	–	–	-64	dB
SINAD	Signal to noise and distortion	–	58	–	dB
ENOB	Effective number of bits	–	9.5	–	bits
Differential Input mode (ADC_CCR.DIFFx = 1)
SNR	Signal to noise ratio	–	64	–	dB
THD	Total harmonic distortion	–	–	-68	dB
SINAD	Signal to noise and distortion	–	62	–	dB
ENOB	Effective number of bits	–	10.5	–	bits