50.7.14 PLLA Characteristics
| Symbol | Parameter | Conditions | Min | Max | Unit |
|---|---|---|---|---|---|
| VDDPLL | Supply voltage range | – | 1.04 | 1.21 | V |
| IVDDPLL | Current consumption(3) | – | 3 | μA/MHz | |
| fIN | Input frequency | – | 32.768 | kHz | |
| fPLLACK | VCO frequency range(1) | – | 380 | 600 | MHz |
| tLOCK | Lock time(3) | – | – | 10 | ms |
| tSTART | Start-up time(3) | – | – | 5 | ms |
Note:
- Internal frequency range of the PLLA. Two output clocks are provided. PLLACK0 and PLLACK1 for core and peripherals frequency selection. Refer to section Power Management Controller (PMC).
- Slow clock crystal oscillator output allowed only.
- Simulation data.
